参数资料
型号: RB80526PZ667256
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370
封装: FCPGA-370
文件页数: 27/74页
文件大小: 502K
代理商: RB80526PZ667256
Datasheet
33
Pentium III Processor for the PGA370 Socket up to 750 MHz
3.0
Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in Table 17, Table 18, and Table 23 ensures that
signal quality effects will not adversely affect processor operation.
3.1
BCLK and PICCLK Signal Quality Specifications and
Measurement Guidelines
Table 17 describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK) and APIC clock (PICCLK) signals. Figure 13 describes the signal quality
waveform for the system bus clock at the processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
Table 17. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins 1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK VIL
0.500
V
13
V1: PICCLK VIL
0.700
V
13
V2: BCLK VIH
2.000
V
13
V2 PICCLK VIH
2.000
V
13
V3: VIN Absolute Voltage Range
–0.58
3.18
V
13
V4: BCLK Rising Edge Ringback
2.000
V
13
2
V4: PICCLK Rising Edge Ringback
2.000
V
13
2
V5: BCLK Falling Edge Ringback
0.500
V
13
2
V5: PICCLK Falling Edge Ringback
0.700
V
13
2
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