- 您现在的位置：买卖IC网 > PDF目录69321 > RB80526PZ667256 (INTEL CORP) 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370 PDF资料下载
参数资料
| 型号： | RB80526PZ667256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FCPGA-370 |
| 文件页数： | 3/74页 |
| 文件大小： | 502K |
| 代理商： | RB80526PZ667256 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页
Datasheet
11
Pentium III Processor for the PGA370 Socket up to 750 MHz
2.0
Electrical Specifications
2.1
Processor System Bus and VREF
The Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology.
The Intel Pentium Pro processor system bus specification is similar to the GTL specification,
but was enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the Intel
Pentium II
Processor Developer’s Manual.
Current P6 family processors vary from the Intel Pentium Pro processor in their output buffer
implementation. The buffers that drive the system bus signals on the Intel CeleronTM, Pentium II,
and Pentium III processors are actively driven to VCCCORE for one clock cycle after the low to high
transition to improve rise times. These signals should still be considered open-drain and require
termination to a supply that provides the high signal level. Because this specification is different
from the standard GTL+ specification, it is referred to as AGTL+, or Assisted GTL+ in this and
other documentation. AGTL+ logic and GTL+ logic are compatible with each other and may both
be used on the same system bus. For more information on AGTL+ routing, see the appropriate
platform design guide.
AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by
the receivers to determine if a signal is a logical 0 or a logical 1, and is supplied by the motherboard
to the PGA370 socket for the processor core. Local VREF copies should also be generated on the
motherboard for all other devices on the AGTL+ system bus. Termination (usually a resistor at
each end of the signal trace) is used to pull the bus up to the high voltage level and to control
reflections on the transmission line. The processor contains on-die termination resistors that
provide termination for one end of the AGTL+ bus, except for RESET#. These specifications
assume another resistor at the end of each signal trace to ensure adequate signal quality for the
AGTL+ signals and provide backwards compatibility for the Intel Celeron processor; see Table 9
for the bus termination voltage specifications for AGTL+. Refer to the Intel Pentium II
Processor Developer’s Manual for the AGTL+ bus specification. Solutions exist for single-ended
termination as well, though this implementation changes system design and eliminate backwards
compatibility for Intel Celeron processors in the PPGA package. Single-ended termination designs
must still provide an AGTL+ termination resistor on the motherboard for the RESET# signal.
Figure 2 is a schematic representation of the AGTL+ bus topology for the Pentium III processors in
the PGA370 socket.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus including trace lengths is highly recommended when designing a system with a heavily
loaded AGTL+ bus, especially for systems using a single set of termination resistors (i.e., those on
the processor die). Such designs will not match the solution space allowed for by installation of
termination resistors on the baseboard.
相关PDF资料 |
PDF描述 |
|---|---|
| RB80526RY001128 | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA370 |
| RB80526RX766128 | 32-BIT, 766 MHz, MICROPROCESSOR, CPGA370 |
| RC5C317B | REAL TIME CLOCK, PDSO14 |
| RC7102 | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| RC7108 | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RB80526PZ733256 | 制造商:Rochester Electronics LLC 功能描述:PIII 733/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ733256S L4CG | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ733256S L4ZL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ800256 | 制造商:Rochester Electronics LLC 功能描述:PIII 800/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ866256 | 制造商:Rochester Electronics LLC 功能描述:PIII 866/133 256K ON DIE FC-PGA - Bulk |
发布紧急采购，3分钟左右您将得到回复。