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参数资料
| 型号： | RB80526PZ667256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FCPGA-370 |
| 文件页数： | 41/74页 |
| 文件大小： | 502K |
| 代理商： | RB80526PZ667256 |
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46
Datasheet
Pentium III Processor for the PGA370 Socket up to 750 MHz
5.2
Processor Markings
The following figure exemplifies the processor top-side markings and it is provided to aid in the
identification of an Pentium III processor for the PGA370 socket. Table 27 lists the measurements
for the package dimensions.
5.3
Processor Signal Listing
Table 29 and Table 30 provide the processor pin definitions. The signal locations on the PGA370
socket are to be used for signal routing, simulation, and component placement on the baseboard.
Figure 20 provides a pin-side view of the Pentium III processor pin-out.
The following notes apply to Table 29 and Table 30:
NOTES:
1. These pins are required for backwards compatibility with other Intel processors. They are not used by the
Pentium III processor. Refer to the appropriate platform design guide and Section 7.1 for implementation
details.
2. RESET# signal must be connected to pins AH4 and X4 for backwards compatibility. Refer to the appropriate
platform design guide and Section 7.1 for implementation details. If backwards compatibility is not required,
then RESET2# (X4) should be connected to GND.
3. VCC1.5V must be supplied by the same voltage source supplying the VTT pins.
4. These VTT pins must be left unconnected (N/C) for backwards compatibility with Intel Celeron processors
(CPUID 066xh). For designs which do not support the Intel Celeron processors (CPUID 066xh), and for
compatibility with future processors, these VTT pins should be connected to the VTT plane. Refer to the
appropriate platform design guide and Section 7.1 for implementation details.
5. This pin is required for backwards compatibility. If backwards compatibility is not required, this pin may be left
connected to VCCCORE. Refer to the appropriate platform design guide for implementation details.
6. Previously, PGA370 designs defined this pin as a GND. It is now reserved and must be left unconnected
(N/C).
7. Previously, PGA370 socket designs defined this pin as a GND. It is now CLKREF.
8. For Uniprocessor designs, this pin is not used and it is defined as RESERVED.
Figure 19. Top Side Processor Markings
Dynamic Production Mark Example
RB80526PY550266
FFFFFFFF-0001 SSSSS
FPO # - S/N
S-spec#
pentium III logo
MALAY
intel
i (m) (c) ’99
Static Mark ink printed at
substrate supplier
Country of Origin
Dynamic Laser Mark
Swatch
Product Code
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| RC5C317B | REAL TIME CLOCK, PDSO14 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RB80526PZ733256 | 制造商:Rochester Electronics LLC 功能描述:PIII 733/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ733256S L4CG | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ733256S L4ZL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ800256 | 制造商:Rochester Electronics LLC 功能描述:PIII 800/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ866256 | 制造商:Rochester Electronics LLC 功能描述:PIII 866/133 256K ON DIE FC-PGA - Bulk |
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