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参数资料
| 型号： | RB80526PZ667256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FCPGA-370 |
| 文件页数： | 20/74页 |
| 文件大小： | 502K |
| 代理商： | RB80526PZ667256 |
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Datasheet
27
Pentium III Processor for the PGA370 Socket up to 750 MHz
NOTE:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported by the
Pentium III processor.
3. Individual processors will only operate at their specified system bus frequency. Either 100 MHz or 133 MHz,
not both.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50
to 1.5V, V
REF at 1.0 V ±2% and with 56 on-die
RTT.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from VREF - 200 mV to VREF + 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 1.0 V swing from VTT - 1V to VTT. This assumes an edge rate of 3V/ns.
9. This should be measured after VCCCORE, VTT, VccCMOS , and BCLK become stable.
10.This specification applies to the Pentium III processor running at 100 MHz system bus frequency.
11. This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
Table 11. Valid System Bus to Core Frequency Ratios 1, 2, 3
Processor
Core Frequency
(MHz)
BCLK Frequency
(MHz)
Frequency
Multiplier
L2 Cache (MHz)
500E
500
100
5
500
533EB
533
133
4
533
550E
550
100
11/2
550
600E
600
100
6
600
600EB
600
133
9/2
600
650
100
13/2
650
667B
667
133
5
667
700
100
7
700
733B
733
133
11/2
733
750
100
15/2
750
Table 12. System Bus AC Specifications (AGTL+ Signal Group)1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
0.40
3.25
ns
7
4, 10, 11
T8: AGTL+ Input Setup Time
BREQ lines
133 MHz
1.20
0.95
ns
8
5, 6, 7, 10
5, 6, 7, 11, 12
T9: AGTL+ Input Hold Time
1.00
ns
8
8, 10
T10: RESET# Pulse Width
1.00
ms
9
6, 9, 10
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RB80526PZ733256 | 制造商:Rochester Electronics LLC 功能描述:PIII 733/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ733256S L4CG | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ733256S L4ZL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ800256 | 制造商:Rochester Electronics LLC 功能描述:PIII 800/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ866256 | 制造商:Rochester Electronics LLC 功能描述:PIII 866/133 256K ON DIE FC-PGA - Bulk |
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