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参数资料
| 型号： | RB80526PZ667256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FCPGA-370 |
| 文件页数： | 8/74页 |
| 文件大小： | 502K |
| 代理商： | RB80526PZ667256 |
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16
Datasheet
Pentium III Processor for the PGA370 Socket up to 750 MHz
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Please refer to the Phase Lock Loop Power section in
the appropriate platform design guide for the recommended filter specifications.
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in Table 6. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot). Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoupling capacitors on all power planes for the processor.
2.4.1
Processor VCC
CORE Decoupling
The regulator for the VCCCORE input must be capable of delivering the dICCCORE/dt (defined in
Table 6) while maintaining the required tolerances (also defined in Table 6). Failure to meet these
specifications can result in timing violations (during VCCCORE sag) or a reduced lifetime of the
component (during VCCCORE overshoot).
2.4.2
Processor System Bus AGTL+ Decoupling
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ bus operation. See the AGTL+ buffer specification in the Intel Pentium II
Processor Developer's Manual for more information. Also, refer to the appropriate platform design
guide for recommended capacitor component placement.
Figure 4. Processor VCCCMOS Package Routing
Intel
Pentium III
Processor
0.1 uF
vcc pkg route
2.5V Supply
2.5V
1.5V Supply
2.5V
VCC
CMOS
*ICH or
Other Logic
CMOS
Pullups
CMOS Signals
Note: *Ensure this logic is compatible
with 1.5V signal levels of the
Intel Pentium III processor
for the PGA370 socket.
相关PDF资料 |
PDF描述 |
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| RC5C317B | REAL TIME CLOCK, PDSO14 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RB80526PZ733256 | 制造商:Rochester Electronics LLC 功能描述:PIII 733/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ733256S L4CG | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ733256S L4ZL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ800256 | 制造商:Rochester Electronics LLC 功能描述:PIII 800/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ866256 | 制造商:Rochester Electronics LLC 功能描述:PIII 866/133 256K ON DIE FC-PGA - Bulk |
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