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参数资料
| 型号： | RB80526PZ667256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 667 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FCPGA-370 |
| 文件页数： | 69/74页 |
| 文件大小： | 502K |
| 代理商： | RB80526PZ667256 |
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Datasheet
71
Pentium III Processor for the PGA370 Socket up to 750 MHz
7.2
Signal Summaries
Table 34 through Table 37 list attributes of the processor output, input, and I/O signals.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TRDY#
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
VID[3:0]
O
The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See Table 2 for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
VCOREDET
O
The VCOREDET pin indicate the type of processor core present. This pin will float for
2.0V VCCCORE based processor and will be shorted to VSS for the Pentium III
processor.
VCC1.5
I
The VCC1.5 V input pin provides the termination voltage for CMOS signals
interfacing to the processor. The Pentium III processor reroutes the 1.5V input to
the VCCCMOS output via the package. The supply for VCC1.5 V must be the same
one used to supply VTT.
VCC2.5
I
The VCC2.5 V input pin provides the termination voltage for CMOS signals
interfacing to processors which require 2.5V termination on the CMOS signals. This
signal is not used by the Pentium III processor.
VCCCMOS
O
The VCCCMOS pin provides the CMOS voltage for use by the platform and is used
for terminating CMOS signals that interface to the processor.
VREF
I
The VREF input pins supply the AGTL+ reference voltage, which is typically 2/3 of
VTT. VREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or a
logical 1.
Table 33. Signal Description (Sheet 8 of 8)
Name
Type
Description
Table 34. Output Signals
Name
Active Level
Clock
Signal Group
CPUPRES#
Low
Asynch
Power/Other
EDGCTRL
N/A
Asynch
Power/Other
FERR#
Low
Asynch
CMOS Output
IERR#
Low
Asynch
CMOS Output
PRDY#
Low
BCLK
AGTL+ Output
TDO
High
TCK
TAP Output
THERMTRIP#
Low
Asynch
CMOS Output
VCOREDET
N/A
Asynch
Power/Other
VID[3:0]
N/A
Asynch
Power/Other
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RB80526PZ733256 | 制造商:Rochester Electronics LLC 功能描述:PIII 733/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ733256S L4CG | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ733256S L4ZL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 0.18um 733MHz 370-Pin FCPGA |
| RB80526PZ800256 | 制造商:Rochester Electronics LLC 功能描述:PIII 800/133 256K ON DIE FC-PGA - Bulk |
| RB80526PZ866256 | 制造商:Rochester Electronics LLC 功能描述:PIII 866/133 256K ON DIE FC-PGA - Bulk |
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