参数资料
型号: RH80532NC021256
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA478
封装: MICRO, FLIP CHIP, PGA-478
文件页数: 10/91页
文件大小: 1142K
代理商: RH80532NC021256
18
Datasheet
Electrical Specifications
2.6
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into groups by
buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference
level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group
as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 4 identifies which signals are common clock, source
synchronous, and asynchronous.
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