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参数资料
| 型号： | RH80532NC021256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FLIP CHIP, PGA-478 |
| 文件页数： | 89/91页 |
| 文件大小： | 1142K |
| 代理商： | RH80532NC021256 |
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Datasheet
9
Introduction
1
Introduction
The mobile Intel Celeron processor on 0.13 micron process and in Micro-FCPGA package
utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package, and plugs into a
surface-mount, Zero Insertion Force (ZIF) socket. The mobile Celeron processor on 0.13 micron
process maintains the tradition of compatibility with IA-32 software. In this document the mobile
Intel Celeron processor on 0.13 micron process and in Micro-FCPGA package will be referred to
as the “mobile Celeron processor” or simply “the processor.”
The mobile Celeron processor is designed for uni-processor based Value PC mobile systems.
Features of the processor include hyper pipelined technology, a 400-MHz FSB, and an execution
trace cache. The 400-MHz FSB is a quad-pumped bus running off a 100-MHz system clock
making 3.2 GB/sec data transfer rates possible. The execution trace cache is a first level cache that
stores approximately 12-k decoded micro-operations, which removes the decoder from the main
execution path.
Additional features include advanced dynamic execution, advanced transfer cache, enhanced
floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced
dynamic execution improves speculative execution and branch prediction internal to the processor.
The advanced transfer cache is a 256-kB, on-die level 2 (L2) cache. The floating point and multi
media units have 128-bit wide registers with a separate register for data movement. Finally, SSE2
support includes instructions for double-precision floating point, SIMD integer, and memory
management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep
Sleep have been incorporated. The processor includes an address bus power down capability which
removes power from the address and data pins when the FSB is not in use. This feature is always
enabled on the processor.
The mobile Celeron processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol.
This FSB is not compatible with the P6 processor family bus. The 400-MHz FSB uses Source-
Synchronous Transfer (SST) of address and data to improve throughput by transferring data four
times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X
address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth
of up to 3.2 Gbytes/second.
The processor FSB uses a variant of GTL+ signalling technology called Assisted Gunning
Transceiver Logic (AGTL+) signal technology. The mobile Celeron processor is available at the
following core frequencies:
2.5 GHz (at 1.30 V)
2.4 GHz (at 1.30 V)
2.2 GHz (at 1.30 V)
2.0 GHz (at 1.30 V)
1.8 GHz (at 1.30 V)
1.7 GHz (at 1.30 V)
1.6 GHz (at 1.30 V)
1.5 GHz (at 1.30 V)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RH80532NC025256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| RH80532NC029256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| RH80532NC033256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| RH80532NC049256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RH80532NC049256S L8SB | 制造商:Intel 功能描述:INTEL CELERON PROCESSOR AVAILABLE AT 1.60 GHZ, 1.8 GHZ, 2.00 GHZ, 2.2 GHZ |
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