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参数资料
| 型号： | RH80532NC021256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FLIP CHIP, PGA-478 |
| 文件页数： | 25/91页 |
| 文件大小： | 1142K |
| 代理商： | RH80532NC021256 |
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Datasheet
31
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
3. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
4. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 7 and with GTLREF
at 2/3 VCC ± 2%.
5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
of 0.4 V/ns to 4.0 V/ns.
6. RESET# can be asserted asynchronously, but must be deasserted synchronously.
7. This should be measured after VCC and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
.
Table 17. FSB Differential Clock Specifications
T# Parameter
Min
Nom
Max
Unit
Figure
Notes1
FSB Frequency
100
MHz
T1: BCLK[1:0] Period
10.0
10.2
ns
2
T2: BCLK[1:0] Period Stability
200
ps
3
T3: BCLK[1:0] High Time
3.94
5
6.12
ns
T4: BCLK[1:0] Low Time
3.94
5
6.12
ns
T5: BCLK[1:0] Rise Time
175
700
ps
4
T6: BCLK[1:0] Fall Time
175
700
ps
4
Table 18. FSB Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes1,2,3
T10: Common Clock Output Valid Delay
0.12
1.55
ns
4
T11: Common Clock Input Setup Time
0.65
ns
5
T12: Common Clock Input Hold Time
0.40
ns
5
T13: RESET# Pulse Width
1
10
ms
6, 7, 8
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