12
Datasheet
Electrical Specifications
the long term reliability of the processor. For further information and design guidelines, refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design
Guide.
2.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current swings when the part is powering on, or entering/exiting low-power states, must be
provided by the voltage regulator solution. For more details on decoupling recommendations,
please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset
Platform Design Guide.
2.3.2
FSB AGTL+ Decoupling
The mobile Celeron processor integrates signal termination on the die and incorporates high
frequency decoupling capacitance on the processor package. Decoupling must also be provided by
the system motherboard for proper AGTL+ bus operation. For more information, refer to the
Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design
Guide.
2.3.3
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.
As in previous generation processors, the mobile Celeron processor core frequency is a multiple of
the BCLK[1:0] frequency. Refer to
Table 2 for the mobile Celeron processor supported ratios.
NOTES:
1. Ratio is used for debug purposes only.
2. Listed frequencies are not necessarily committed production frequencies.
The mobile Celeron processor uses a differential clocking implementation.
Table 2.
Core Frequency to FSB Multipliers
Core Frequency
Multiplication of System Core
Frequency to FSB Frequency
Notes2
800 MHz
1/8
1
1.20 GHz
1/12
1.40 GHz
1/14
1.50 GHz
1/15
1.60 GHz
1/16
1.70 GHz
1/17
1.80 GHz
1/18
2.00 GHz
1/20
2.20 GHz
1/22
2.40 GHz
1/24
2.50 GHz
1/25