参数资料
型号: RH80532NC021256
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA478
封装: MICRO, FLIP CHIP, PGA-478
文件页数: 27/91页
文件大小: 1142K
代理商: RH80532NC021256
Datasheet
33
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All
Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge
at 0.5*VCC
3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion and before the deassertion of PROCHOT# for the processor to complete current instruction
execution. This specification refers to PROCHOT# when asserted by the processor. There are no pulse width
requirements for when PROCHOT# is asserted by the system.
6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
Table 20. Miscellaneous Signals AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes1,2,3,6
T35: Asynch GTL+ Input Pulse Width
2
BCLKs
T36: PWRGOOD to RESET# de-assertion
time
110
ms
T37: PWRGOOD Inactive Pulse Width
10
BCLKs
4
T38: PROCHOT# pulse width
500
us
5
T39: THERMTRIP# to Vcc Removal
0.5
s
T40: FERR# Valid Delay from STPCLK#
deassertion
05
BCLKs
Table 21. FSB AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Setup Time
4BCLKs
1
T46: Reset Configuration Signals (A[31:3]#,
BR0#, INIT#, SMI#) Hold Time
220
BCLKs
2
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