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| 型号： | RH80532NC021256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FLIP CHIP, PGA-478 |
| 文件页数： | 11/91页 |
| 文件大小： | 1142K |
| 代理商： | RH80532NC021256 |
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Datasheet
19
Electrical Specifications
NOTES:
1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must
be terminated on the system board. Refer to Section 2.5 and the Mobile Intel
Pentium
4 Processor-M and
Intel
845MP/845MZ Chipset Platform Design Guide for termination requirements and further details.
5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 7.1 for details.
Table 4.
FSB Pin Groups
Signal Group
Type
Signals1
AGTL+ Common Clock Input
Common
clock
BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2,
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,
MCERR#
AGTL+ Source Synchronous
I/O
Source
Synchronous
AGTL+ Strobes
Common
Clock
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+ Input4,5
Asynchronous
A20M#, DPSLP#, IGNNE#, INIT#5, LINT0/INTR, LINT1/
NMI, SMI#5, SLP#, STPCLK#
Asynchronous GTL+ Output4
Asynchronous
FERR#/PBE#, IERR#2, THERMTRIP#, PROCHOT#
TAP Input4
Synchronous
to TCK
TCK, TDI, TMS, TRST#
TAP Output4
Synchronous
to TCK
TDO
FSB Clock
N/A
BCLK[1:0], ITP_CLK[1:0]3
Power/Other
N/A
V
CC, VCCA, VCCIOPLL, VCCVID, VID[4:0], VSS, VSSA,
GTLREF[3:0], COMP[1:0], NC, TESTHI[5:0],
TESTHI[10:8], TESTHI[11], ITPCLKOUT[1:0],
PWRGOOD, THERMDA, THERMDC, SKTOCC#,
VCC_SENSE, VSS_SENSE, BSEL[1:0], DBR#
3
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#5
ADSTB0#
A[35:17]#5
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
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