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| 型号： | RH80532NC021256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FLIP CHIP, PGA-478 |
| 文件页数： | 40/91页 |
| 文件大小： | 1142K |
| 代理商： | RH80532NC021256 |
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Datasheet
45
FSB Signal Quality Specifications
3
FSB Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI)
effects. For these reasons, it is important that the designer work to achieve a solution that provides
acceptable signal quality across all systematic variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and for interpreting results for signal quality measurements of actual designs.
The mobile Celeron processor IBIS models should be used while performing signal integrity
simulations.
3.1
FSB Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines
Table 25 describes the signal quality specifications at the processor pads for the processor FSB
clock (BCLK) signals. Figure 23 describes the signal quality waveform for the FSB clock at the
processor pads.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all mobile Celeron processor frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Table 25. BCLK Signal Quality Specifications
Parameter
Min
Max
Unit
Figure
Notes1
BCLK[1:0] Overshoot
N/A
0.30
V
BCLK[1:0] Undershoot
N/A
0.30
V
BCLK[1:0] Ringback Margin
0.20
N/A
V
2
BCLK[1:0] Threshold Region
N/A
0.10
V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RH80532NC025256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| RH80532NC029256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| RH80532NC033256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| RH80532NC049256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RH80532NC049256S L8SB | 制造商:Intel 功能描述:INTEL CELERON PROCESSOR AVAILABLE AT 1.60 GHZ, 1.8 GHZ, 2.00 GHZ, 2.2 GHZ |
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