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参数资料
型号： S29CD032G0RFFN003
厂商： SPANSION LLC
元件分类： PROM
英文描述： 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80
封装： 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80
文件页数： 18/81页
文件大小： 1276K
代理商： S29CD032G0RFFN003
March 3, 2009 S29CD-G_00_B1
S29CD-G Flash Family
23
Da ta
Shee t
(Prelim i nar y )
12.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
Address access time (tACC) is the delay from stable addresses to valid output data. The chip enable access
time (tCE) is the delay from stable addresses and stable CE# to valid data at the output pins. The output
enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output pins (assuming
the addresses were stable for at least tACC–tOE time and CE# is asserted for at least tCE–tOE time).
See Reading Array Data in Non-burst Mode on page 40 and Reading Array Data in Burst Mode on page 40
for more information. Refer to Asynchronous Read Operations on page 63 for timing specifications and to
Figure 24.2 on page 64 for the timing diagram. ICC1 in DC Characteristics on page 60 represents the active
current specification for reading array data.
12.3
Simultaneous Read/Write Operations Overview
12.3.1
Overview
The Simultaneous Read/Write feature allows embedded program or embedded erase operation to be
executed in the Small Bank, while reading from the Large Bank. The opposite case is not valid.
Note
Please refer to the Memory Map Table 11.1 on page 18, Table 11.2 on page 19, Table 11.3 on page 20, and Table 11.4 on page 21 for
Small and Large Bank assignments.
12.3.2
Program/Erase Suspend and Simultaneous Operation
There is no restriction to implementing a program-suspend or erase-suspend during a simultaneous
operation.
12.3.3
Common Flash Interface (CFI) and Password Program/Verify and
Simultaneous Operation
Simultaneous read/write operation is disabled during the CFI and Password Program/Verify operation,
including PPB program/erase and unlocking a password operation. Only array data can be read in the Large
Bank during a simultaneous operation.
Table 12.2 Allowable Conditions for Simultaneous Operation
Small Bank
Large Bank
Embedded Erase
Burst (Synchronous) Read or Asynchronous Read
Embedded Program
Burst (Synchronous) Read or Asynchronous Read
相关PDF资料
PDF描述
S29CD032G0RQFI012 1M X 32 FLASH 2.7V PROM, 48 ns, PQFP80
S29CL032J0JFAM020 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
S29CL032J0JFFM020 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
S29CL032J0RFAM012 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80
S29GL032A10TAIR11 Ceramic Chip Capacitors / High Voltage; Capacitance [nom]: 3.3pF; Working Voltage (Vdc)[max]: 500V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder (SnPb) Plated Nickel Barrier; Body Dimensions: 0.079" x 0.049"; Container: Bulk; Features: High Voltage; Unmarked
相关代理商/技术参数
参数描述
S29CD032J0MQAN010 制造商:Spansion 功能描述:
S29CD032J0MQFM010U 制造商:Spansion 功能描述:N/A - Trays
S29CD032J0PFAM010 制造商:Spansion 功能描述:
S29CD032J0PQFI010 制造商:Spansion 功能描述:AUTO 3.3V 512KX32 FLASH - Trays
S29CL016J0JQFM030 制造商:Spansion 功能描述:FLASH PARALLEL 3.3V 16MBIT 512KX32 54NS 80PQFP - Trays
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