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参数资料
| 型号： | S29CD032G0RFFN003 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 50/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD032G0RFFN003 |
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52
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
Legend
BA = Bank Address. The set of addresses that comprise a bank. The system may write any address within a bank to identify that bank for a command.
PA = Program Address (Amax–A0). Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
RA = Read Address (Amax–A0).
RD = Read Data. Data DQmax–DQ0 at address location RA.
SA = Sector Address. The set of addresses that comprise a sector. The system may write any address within a sector to identify that sector for a command.
WD = Write Data. See Configuration Register on page 30 definition for specific write data. Data latched on rising edge of WE#.
X = Don’t care
Notes
1. See Table 12.1 on page 22 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher
than DQ7 are don’t cares.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect
mode, or if DQ5 goes high (while the bank is providing status information).
7. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID or device ID
information. See Autoselect Command on page 41 for more information.
8. This command cannot be executed until The Unlock Bypass command must be executed before writing this command sequence. The Unlock Bypass Reset
command must be executed to return to normal operation.
9. This command is ignored during any embedded program, erase or suspended operation.
10. Valid read operations include asynchronous and burst read mode operations.
11. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering option 01.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Program/Erase Suspend mode. The Program/Erase
Suspend command is valid only during a sector erase operation, and requires the bank address.
13. The Program/Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at VID during the entire operation of this command.
17. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation.
18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode.
Table 15.2 Memory Array Command Definitions
Command (Notes)
Cyc
les
Bus Cycles (Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (5)
1
RA
RD
Reset (6)
1XXX
F0
Autoselect
Manufacturer ID
4
555
AA
2AA
55
555
90
BA+X00
01
Device ID (11)
6
555
AA
2AA
55
555
90
BA+X01
7E
BA+X0E
09 for
32 Mb
36 or
08 for
16 Mb
BA+X0F
00/01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (12)
1BA
B0
Program/Erase Resume (13)
1BA
30
55
98
Accelerated Program (16)
2XX
A0
PA
PD
Configuration Register Verify (15)
3
555
AA
2AA
55
BA+555
C6
BA+XX
RD
Configuration Register Write (17)
4
555
AA
2AA
55
555
D0
XX
WD
Unlock Bypass Entry (18)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (18)
2XX
A0
PA
PD
Unlock Bypass Erase (18)
2XX
80
XX
10
XX
98
Unlock Bypass Reset (18)
2XX
90
XX
00
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