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参数资料
| 型号： | S29CD032G0RFFN003 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 22/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD032G0RFFN003 |
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March 3, 2009 S29CD-G_00_B1
S29CD-G Flash Family
27
Da ta
Shee t
(Prelim i nar y )
12.10 Synchronous (Burst) Read Operation
The device is capable of performing burst read operations to improve total system data throughput. The 2, 4,
and 8 double word accesses are configurable as linear burst accesses. All burst operations provide wrap
around linear burst accesses. Additional options for all burst modes include initial access delay configurations
(2–16 CLKs) Device configuration for burst mode operation is accomplished by writing the Configuration
Register with the desired burst configuration information. Once the Configuration Register is written to enable
burst mode operation, all subsequent reads from the array are returned using the burst mode protocols. Like
the main memory access, the Secured Silicon Sector memory is accessed with the same burst or
asynchronous timing as defined in the Configuration Register. However, the user must recognize burst
operations past the 256 byte Secured Silicon boundary returns invalid data.
Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection
bits are treated as single cycle reads, even when burst mode is enabled. Read operations to these locations
results in the data remaining valid while OE# is at VIL, regardless of the number of CLK cycles applied to the
device.
12.11 Linear Burst Read Operations
Linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32 bits). (See Table 12.4 for all
valid burst output sequences). The IND/WAIT# pin transitions active (VIL) during the last transfer of data
during a linear burst read before a wrap around, indicating that the system should initiate another ADV# to
start the next burst access. If the system continues to clock the device, the next access wraps around to the
starting address of the previous burst access. The IND/WAIT# signal remains inactive (floating) when not
active. See Table 12.4 for a complete 32 data bus interface order.
12.11.1
CE# Control in Linear Mode
The CE# (Chip Enable) pin enables the device during read mode operations. CE# must meet the required
burst read setup times for burst cycle initiation. If CE# is taken to VIH at any time during the burst linear or
burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal. Restarting a burst
cycle is accomplished by taking CE# and ADV# to VIL.
12.11.2
ADV# Control In Linear Mode
The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock edge when CE# and ADV#
are at VIL and the device is configured for either linear burst mode operation. A burst access is initiated and
the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge,
whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the
previous address is discarded and subsequent burst transfers are invalid until ADV# transitions to VIH before
a clock edge, which initiates a new burst sequence.
Table 12.4 32- Bit Linear and Burst Data Order
Data Transfer Sequence (Independent of the WORD# pin)
Output Data Sequence (Initial Access Address)
Two Linear Data Transfers
0-1 (A0 = 0)
1-0 (A0 = 1)
Four Linear Data Transfers
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
2-3-0-1 (A:A-1/A1-A0 = 10)
3-0-1-2 (A0:A-1/A1-A0 = 11)
Eight Linear Data Transfers
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
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