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参数资料
| 型号： | S29CD032G0RFFN003 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 25/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD032G0RFFN003 |
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March 3, 2009 S29CD-G_00_B1
S29CD-G Flash Family
29
Da ta
Shee t
(Prelim i nar y )
12.11.6
Burst Access Timing Control
In addition to the IND/WAIT# signal control, burst controls exist in the Control Register for initial access delay,
delivery of data on the CLK edge, and the length of time data is held.
12.11.7
Initial Burst Access Delay Control
The device contains options for initial access delay of a burst access. The initial access delay has no effect on
asynchronous read operations.
Burst Initial Access Delay is defined as the number of clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid.
The burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or
upon a rising ADV# edge, whichever comes first. (Table 12.6 describes the initial access delay
configurations.)
Figure 12.3 Initial Burst Delay Control
Notes
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or five clock cycles
12.11.8
Burst CLK Edge Data Delivery
The device delivers data on the rising of CLK. Bit 6 in the Control Register (CR6) is set to 1, and is the default
configuration.
Table 12.6 Burst Initial Access Delay
CR13
CR12
CR11
CR10
Initial Burst Access (CLK cycles)
40 MHz (0J), 56 MHz (0M), 66 MHz (0P),
75 MHz (0R, 32 Mb only)
0000
2
0001
3
0010
4
0011
5
0100
6
0101
7
0
110
8
0111
9
CLK
ADV#
Addresses
DQ31-DQ03
DQ31-DQ04
DQ31-DQ05
Valid Address
Three CLK Delay
2nd CLK
3rd CLK
4th CLK
5th CLK
1st CLK
Four CLK Delay
Address 1 Latched
Five CLK Delay
D0
D1
D2
D3
D0
D1
D2
D0
D1
D2
D3
D4
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