- 您现在的位置：买卖IC网 > PDF目录225140 > S29CD032G0RFFN003 (SPANSION LLC) 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 PDF资料下载
参数资料
| 型号： | S29CD032G0RFFN003 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 19/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD032G0RFFN003 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页
24
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
12.4
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. See
Sector Erase and Program Suspend Command on page 45 for details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 11.1 on page 18 to
Table 11.4 on page 21 indicate the address space that each sector occupies. A sector address consists of
the address bits required to uniquely select a sector. See Command Definitions on page 40 for details on
erasing a sector or the entire chip, or suspending/resuming the erase operation.
When in Synchronous read mode configuration, the device is able to perform both asynchronous and
synchronous write operations. CLK and ADV# address latch is supported in synchronous programming
mode. During a synchronous write operation, to write a command or command sequence, (which includes
programming data to the device and erasing sectors of memory), the system must drive ADV# and CE# to
VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and CE# to
VIH, when writing commands or data.
12.4.1
Accelerated Program and Erase Operations
The device offers accelerated program/erase operations through the ACC pin. When the system asserts VHH
(12V) on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write
the two-cycle Unlock Bypass program command sequence to do accelerated programming. The device uses
the higher voltage on the ACC pin to accelerate the operation. A sector that is being protected with the WP#
pin is protected during accelerated program or Erase.
Note
The ACC pin must not be at VHH during any operation other than accelerated programming, or device damage can result.
12.4.2
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–
DQ0. Standard read cycle timings apply in this mode. See Autoselect Mode on page 25 and Autoselect
Command on page 41 for more information.
12.5
Automatic Sleep Mode (ASM)
The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the
device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep
mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always available to
the system. While in synchronous mode, the device automatically enables this mode when either the first
active CLK level is greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst operation is
required to provide new data.
相关PDF资料 |
PDF描述 |
|---|---|
| S29CD032G0RQFI012 | 1M X 32 FLASH 2.7V PROM, 48 ns, PQFP80 |
| S29CL032J0JFAM020 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL032J0JFFM020 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL032J0RFAM012 | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| S29GL032A10TAIR11 | Ceramic Chip Capacitors / High Voltage; Capacitance [nom]: 3.3pF; Working Voltage (Vdc)[max]: 500V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder (SnPb) Plated Nickel Barrier; Body Dimensions: 0.079" x 0.049"; Container: Bulk; Features: High Voltage; Unmarked |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S29CD032J0MQAN010 | 制造商:Spansion 功能描述: |
| S29CD032J0MQFM010U | 制造商:Spansion 功能描述:N/A - Trays |
| S29CD032J0PFAM010 | 制造商:Spansion 功能描述: |
| S29CD032J0PQFI010 | 制造商:Spansion 功能描述:AUTO 3.3V 512KX32 FLASH - Trays |
| S29CL016J0JQFM030 | 制造商:Spansion 功能描述:FLASH PARALLEL 3.3V 16MBIT 512KX32 54NS 80PQFP - Trays |
发布紧急采购，3分钟左右您将得到回复。