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参数资料
| 型号： | S29CD032G0RFFN003 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 20/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD032G0RFFN003 |
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March 3, 2009 S29CD-G_00_B1
S29CD-G Flash Family
25
Da ta
Shee t
(Prelim i nar y )
12.5.1
Standby Mode
When the system is not responding or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at Vcc
± 0.2 V.
The device requires standard access time (tCE) for read access, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Caution: entering the standby mode via the RESET# pin also resets the device to the read mode and floats
the data I/O pins. Furthermore, entering ICC7 during a program or erase operation leaves erroneous data in
the address locations being operated on at the time of the RESET# pulse. These locations require updating
after the device resumes standard operations. See RESET#: Hardware Reset Pin on page 25 for further
discussion of the RESET# pin and its functions.
12.6
RESET#: Hardware Reset Pin
The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic 0 on
this pin forces the device out of any mode that is currently executing back to the reset state. The RESET# pin
may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential
bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data output
pins for the duration of the RESET pulse. All pins are don’t cares during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset
operation is internally complete. This action requires between 1 s and 7s for either Chip Erase or Sector
Erase. The RY/BY# pin can be used to determine when the reset operation is complete. Otherwise, allow for
the maximum reset time of 11 s. If RESET# is asserted when a program or erase operation is not executing
(RY/BY# = 1), the reset operation completes within 500 ns. The Simultaneous Read/Write feature of this
device allows the user to read a bank after 500 ns if the bank was in the read/reset mode at the time RESET#
was asserted. If one of the banks was in the middle of either a program or erase operation when RESET#
was asserted, the user must wait 11 s before accessing that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the address
locations being operated on at the time of device reset. These locations need updating after the reset
operation is complete. See Figure 24.6 on page 67 for timing specifications.
Asserting RESET# active during VCC and VIO power up is required to guarantee proper device initialization
until VCC and VIO reaches steady state voltages.
12.7
Output Disable Mode
See Table 12.1 on page 22 Device Bus Operation for OE# Operation in Output Disable Mode.
12.8
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6,
A1, and A0 must be as shown in Table 11.2 on page 19 (top boot devices) or Table 11.3 on page 20 (bottom
boot devices). In addition, when verifying sector protection, the sector address must appear on the
appropriate highest order address bits (see Table 11.1 on page 18 through Table 11.4 on page 21).
Table 12.3 on page 26 shows the remaining address bits that are don’t care. When all necessary bits are set
as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command. This method does not require VID. See Command Definitions on page 40 for details on using the
autoselect mode.
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