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参数资料
| 型号： | S29CD032G0RFFN003 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 32/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD032G0RFFN003 |
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36
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
13.7
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking
Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates the device is in Password
Protection Mode, the PPB Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset.
The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password
Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing
for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the
PPB Lock Bit Set command sets the PPB Lock Bit back to a 1.
If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is
cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command.
Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The
Password Unlock command is ignored in Persistent Sector Protection Mode.
13.8
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes. In addition, the following hardware data protection measures prevent accidental
erasure or programming, which might otherwise be caused by spurious system level signals during VCC
power-up and power-down transitions, or from system noise.
13.8.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal erase/program circuits are disabled, and
the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
13.8.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle.
13.8.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH).
13.8.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power-up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
13.8.5
VCC and VIO Power-up And Power-down Sequencing
The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Asserting RESET#
to VIL is required during the entire VCC and VIO power sequence until the respective supplies reach the
operating voltages. Once, VCC and VIO attain the operating voltages, de-assertion of RESET# to VIH is
permitted.
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