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参数资料
| 型号： | S29CD032G0RFFN003 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 48 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 52/81页 |
| 文件大小： | 1276K |
| 代理商： | S29CD032G0RFFN003 |
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54
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
16. Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 16.1 on page 58 and the following subsections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
16.1
DQ7: Data# Polling
The device features a Data# polling flag as a method to indicate to the host system whether the embedded
algorithms are in progress or are complete. During the Embedded Program Algorithm, an attempt to read the
bank in which programming was initiated produces the complement of the data last written to DQ7. Upon
completion of the Embedded Program Algorithm, an attempt to read the device produces the true last data
written to DQ7. Note that DATA# polling returns invalid data for the address being programmed or erased.
For example, the data read for an address programmed as 0000 0000 1000 0000b, returns
XXXX XXXX 0XXX XXXXb during an Embedded Program operation. Once the Embedded Program
Algorithm is complete, the true data is read back on DQ7. Note that at the instant when DQ7 switches to true
data, the other bits may not yet be true. However, they are all true data on the next read from the device.
Please note that Data# polling may give misleading status when an attempt is made to write to a protected
sector.
For chip erase, the Data# polling flag is valid after the rising edge of the sixth WE# pulse in the six write pulse
sequence. For sector erase, the Data# polling is valid after the last rising edge of the sector erase WE# pulse.
Data# polling must be performed at sector addresses within any of the sectors being erased and not a sector
that is a protected sector. Otherwise, the status may not be valid. DQ7 = 0 during an Embedded Erase
Algorithm (chip erase or sector erase operation), but returns a 1 after the operation completes because it
drops back into read mode.
In asynchronous mode, just prior to the completion of the Embedded Algorithm operations, DQ7 may change
asynchronously while OE# is asserted low. (In synchronous mode, ADV# exhibits this behavior.) The status
information may be invalid during the instance of transition from status information to array (memory) data. An
extra validity check is therefore specified in the data polling algorithm. The valid array data on DQ31–DQ0 is
available for reading on the next successive read attempt.
The Data# polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, Erase Suspend-Program mode, or sector erase time-out.
If the user attempts to write to a protected sector, Data# polling is activated for about 1 s: the device then
returns to read mode, with the data from the protected sector unchanged. If the user attempts to erase a
protected sector, Toggle Bit (DQ6) is activated for about 150 s; the device then returns to read mode,
without having erased the protected sector.
Table 16.1 on page 58 shows the outputs for Data# Polling on DQ7. Figure 16.1 on page 55 shows the
Data# Polling algorithm. Figure 24.10 on page 70 shows the timing diagram for synchronous status DQ7
data polling.
16.2
RY/BY#: Ready/Busy#
The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or completed. If the output is low, the device is busy with either a
program, erase, or reset operation. If the output is floating, the device is ready to accept any read/write or
erase operation. When the RY/BY# pin is low, the device does not accept any additional program or erase
commands with the exception of the Erase suspend command. If the device enters Erase Suspend mode, the
RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising edge of the
fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/BY# is valid after the rising edge of
the sixth WE# pulse in the six write pulse sequence. For sector erase, the RY/BY# is also valid after the rising
edge of the sixth WE# pulse.
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