- 您现在的位置：买卖IC网 > PDF目录297343 > S71JL064H80BFI122 (ADVANCED MICRO DEVICES INC) SPECIALTY MEMORY CIRCUIT, PBGA73 PDF资料下载
参数资料
| 型号： | S71JL064H80BFI122 |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封装： | 11.60 X 8 MM, FBGA-73 |
| 文件页数： | 60/95页 |
| 文件大小： | 2244K |
| 代理商： | S71JL064H80BFI122 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页当前第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页
February 25, 2004 S71JLxxxHxx_00A1
S29JL064H
63
Pre l i m i n a r y
5 illustrates the algorithm for the erase operation. Refer to the "Erase and Pro-
gram Operations" section tables in the AC Characteristics section for parameters,
and Figure 20 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock cycles are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table 11 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Em-
bedded Erase algorithm automatically programs and verifies the entire sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 80 s occurs.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 80 s, otherwise erasure
may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is written. Any com-
mand other than Sector Erase or Erase Suspend during the time-out
period resets that bank to the read mode. The system must rewrite the com-
mand sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out
(See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# or CE# pulse (first rising edge) in the command
sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading
array data and addresses are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the "Write Operation
Status" section section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is
valid. All other commands are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has returned to reading
array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and
CFI functions are unavailable when an erase operation is in progress.
5 illustrates the algorithm for the erase operation. Refer to the "Erase and Pro-
gram Operations" section tables in the AC Characteristics section for parameters,
and Figure 20 section for timing diagrams.
相关PDF资料 |
PDF描述 |
|---|---|
| S71JL064H80BAI020 | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| S71WS512NC0BAWEK2 | Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BAWEK3 | Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BAWEN0 | Stacked Multi-Chip Product (MCP) |
| S71WS512NC0BAWEN2 | Stacked Multi-Chip Product (MCP) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S71KL512SC0BHV000 | 功能描述:IC 512MB FLASH 64MB DRAM 24FBGA 制造商:cypress semiconductor corp 系列:HyperFlash? + HyperRAM? KL 包装:托盘 零件状态:在售 格式 - 存储器:多芯（FLASH/RAM） 存储器类型:FLASH + DRAM 存储容量:512Mbit Flash, 64Mbit RAM 速度:100MHz 接口:并联，串行 电压 - 电源:2.7 V ~ 3.6 V 工作温度:-40°C ~ 105°C（TA） 封装/外壳:24-VBGA 供应商器件封装:24-FBGA（6x8） 标准包装:338 |
| S71NS032J80 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71NS032J80BJWRA | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71NS032JA0 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
| S71NS032JA0BJWRT | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) |
发布紧急采购，3分钟左右您将得到回复。