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| 型号： | S71JL064H80BFI122 |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封装： | 11.60 X 8 MM, FBGA-73 |
| 文件页数： | 68/95页 |
| 文件大小： | 2244K |
| 代理商： | S71JL064H80BFI122 |
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70
S29JL064H
S71JLxxxHxx_00A1 February 25, 2004
Pr el i m i n ary
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 12 to compare outputs for DQ2 and DQ6.
7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle
Bit II” explains the algorithm. See also the "DQ6: Toggle Bit I" section subsection.
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 7. Toggle Bit Algorithm
START
No
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle?
Read Byte Twice
(DQ7–DQ0)
Address = VA
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
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