参数资料
型号: AD9992BBCZ
厂商: Analog Devices Inc
文件页数: 17/92页
文件大小: 0K
描述: IC CCD SGNL PROC 12BIT 105CSPBGA
产品变化通告: AD9992 Discontinuation 22/Feb/2012
标准包装: 1
类型: CCD 信号处理器,12 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
电流 - 电源: 27mA
安装类型: 表面贴装
封装/外壳: 105-LFBGA,CSPBGA
供应商设备封装: 105-CSPBGA(8x8)
包装: 托盘
AD9992
Rev. C | Page 24 of 92
HBLK
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER
H1/H3
H2/H4
1/FPIX
2 × (1/FPIX)
05
89
1-
0
28
Figure 28. Generating Wide H-Clock Pulses During HBLK Interval
H1
H2
HBLKSTART
A
HBLKEND
REPEAT AREA 0
HD
B
C
REPEAT AREA 1 REPEAT AREA 2 REPEAT AREA 3
REPEAT AREA 4 REPEAT AREA 5
MASK A, B, C PULSES IN ANY REPEAT
AREA BY SETTING RA*H*REP* = 0
CHANGE NUMBER OF A, B, C PULSES IN ANY
REPEAT AREA USING RA*H*REP* REGISTERS
CREATE UP TO 3 GROUPS OF TOGGLES
A, B, C COMMON IN ALL REPEAT AREAS
05
89
1-
0
29
Figure 29. HBLK Mode 2 Operation
HBLK
H1
H2
HBLKSTART
HBLKSTARTA
HBLKEND
HBLKLEN
REPEAT AREA 0
HBLKREP = 2
TO CREATE TWO REPEAT AREAS
HD
REPEAT AREA 1
HBLKSTARTB
HBLKSTARTC
RA0H1REPA RA0H1REPB
RA0H1REPC
ALL RA*H*REPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES
RA1H1REPA RA1H1REPB
RA1H1REPC
RA0H2REPA RA0H2REPB
RA0H2REPC
RA1H2REPA RA1H2REPB
RA1H2REPC
0589
1-
0
30
Figure 30. HBLK Mode 2 Registers
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