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参数资料
| 型号： | AD9992BBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/92页 |
| 文件大小： | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 产品变化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 标准包装： | 1 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 27mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 托盘 |
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AD9992
Rev. C | Page 31 of 92
Register
Length
Description
VREPA_3
13b
Number of repetitions for the V-Pattern Group A for third lines.
VREPA_4
13b
Number of repetitions for the V-Pattern Group A for fourth lines.
VREPB_ODD
13b
Number of repetitions for the V-Pattern Group B for odd lines.
VREPC_ODD
13b
Number of repetitions for the V-Pattern Group C for odd lines.
VREPD_ODD
13b
Number of repetitions for the V-Pattern Group D for odd lines.
VREPB_EVEN
13b
Number of repetitions for the V-Pattern Group B for even lines.
VREPC_EVEN
13b
Number of repetitions for the V-Pattern Group C for even lines.
VREPD_EVEN
13b
Number of repetitions for the V-Pattern Group D for even lines.
FREEZE1
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_EVEN [12:0] register
when special VSEQALT_EN mode is enabled.
FREEZE2
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_EVEN [12:0] register
when special VSEQALT_EN mode is enabled.
FREEZE3
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_ODD [12:0] register
when special VSEQALT_EN mode is enabled.
FREEZE4
13b
Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_ODD [12:0] register
when special VSEQALT_EN mode is enabled.
RESUME1
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_EVEN [17:13]
register when S within line for each XV1 to XV24 output when special VSEQALT_EN mode is enabled.
RESUME2
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_EVEN [17:13]
register when special VSEQALT_EN mode is enabled.
RESUME3
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_ODD [17:13]
register when special VSEQALT_EN mode is enabled.
RESUME4
13b
Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_ODD [17:13]
register when special VSEQALT_EN mode is enabled.
LASTREPLEN_A
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENA register.
LASTREPLEN_B
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENB register.
LASTREPLEN_C
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENC register.
LASTREPLEN_D
13b
Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLEND register.
LASTTOG_A
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
LASTTOG_B
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
LASTTOG_C
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
LASTTOG_D
13b
Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN.
Note that the toggle position is common for all vertical signals.
VSEQALT_EN
1b
Special V-sequence alternation mode is enabled when this register is programmed high.
VALT_MAP
1b
Enables the use of FREEZE/RESUME register locations to specify the VALTSEL0 and VALTSEL1 registers. Must be
enabled if VSEQALT mode is enabled.
VALTSEL0_EVEN
18b
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D into
unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
VALTSEL1_EVEN
18b
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D into
unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
VALTSEL0_ODD
18b
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D into
unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
VALTSEL1_ODD
18b
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D into
unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments.
SPC_PAT_EN
1b
Enable special V-pattern to be inserted into one repetition of a VPATA series.
SPC_PAT_EN [0]: Set to 1 to enable VPATB to be used as special pattern insertion.
SPC_PAT_EN [1]: Set to 1 to enable VPATC to be used as special pattern insertion.
SPC_PAT_EN [2]: Set to 1 to enable VPATD to be used as special pattern insertion.
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| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 传感器和探测器接口 系列:- 其它有关文件:Automotive Product Guide 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:74 系列:- 类型:触控式传感器 输入类型:数字 输出类型:数字 接口:JTAG，串行 电流 - 电源:100µA 安装类型:表面贴装 封装/外壳:20-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:20-TSSOP 包装:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:在售 类型:ADC，DAC 输入类型:LVDS 输出类型:LVDS 接口:SPI 电流 - 电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:196-LFBGA，CSPBGA 供应商器件封装:196-CSPBGA（12x12） 标准包装:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:在售 类型:ADC，DAC 输入类型:LVDS 输出类型:LVDS 接口:SPI 电流 - 电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:196-LFBGA，CSPBGA 供应商器件封装:196-CSPBGA（12x12） 标准包装:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件状态:在售 标准包装:1 |
| AD9994 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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