参数资料
型号: AD9992BBCZ
厂商: Analog Devices Inc
文件页数: 28/92页
文件大小: 0K
描述: IC CCD SGNL PROC 12BIT 105CSPBGA
产品变化通告: AD9992 Discontinuation 22/Feb/2012
标准包装: 1
类型: CCD 信号处理器,12 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
电流 - 电源: 27mA
安装类型: 表面贴装
封装/外壳: 105-LFBGA,CSPBGA
供应商设备封装: 105-CSPBGA(8x8)
包装: 托盘
AD9992
Rev. C | Page 34 of 92
XV1
XV2
XV23
VLENA
VLENB
VLENC
VLEND
V-PATTERN A
XV3
V-PATTERN B
V-PATTERN C
V-PATTERN D
NOTES
1. EACH SEGMENT MUST BE THE SAME LENGTH.
VLENA = VLENB = VLENC = VLEND.
05
89
1-
03
9
Figure 39. Vertical Timing Divided Into Four Segments: VPATA, VPATB, VPATC, and VPATD
HD
COMBINED
V-PATTERN
NOTES
1. ABLE TO CONCATENATE PATTERNS TOGETHER ARBITRARILY.
2. EACH PATTERN CAN HAVE UP TO FOUR TOGGLES PROGRAMMED.
3. MAY CONCATENATE UP TO 18 PATTERNS INTO A MERGED PATTERN.
4. ODD AND EVEN LINES CAN HAVE A DIFFERENT PATTERN CONCATENATION
SPECIFIED BY VALTSEL EVEN AND ODD REGISTERS.
A B B DACC A
B C B DAB A A
05
89
1-
04
0
Figure 40. Concatenating Each VPAT Group in Arbitrary Order
NOTES
1. SIX V-PATTERN SEGMENTS CONCATENATED INTO A MERGED PATTERN.
2. COMMON AND REPETITIVE VTP SEGMENTS DERIVED FROM THE COMPLETE VTP PATTERN.
3. VALTSEL REGISTERS SPECIFY SEGMENT ORDER TO CREATE THE CONCATENATED MERGED PATTERN.
AC
B
D
XV1
XV2
XV23
XV3
VPATA
VPATC
VPATB
VPATD
VPATA
VALTSEL0_EVEN
0
1
0
VALTSEL1_EVEN
0
1
0
1
0
SEGMENT 1
A
D
XV1 TO XV23
SEGMENT 2
SEGMENT 3
SEGMENT4
SEGMENT 5
SEGMENT 6
HD
05
89
1-
0
41
Figure 41. Special V-Sequence Alternation Mode Using VALTSEL Registers to Specify Segment Order
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