参数资料
型号: COREFIR-RM
厂商: Microsemi SoC
文件页数: 14/67页
文件大小: 0K
描述: IP MODULE COREFIR
标准包装: 1
系列: *
Filter Description
Reloadable Coefficient Mode
Figure 11 shows a functional block diagram for Reloadable Coefficient mode. This mode uses two memory
pages: active and auxiliary. The active page comprises Storage registers connected to the multiplier
coefficient inputs. The auxiliary page implements a multi-bit Shift register. Once a new coefficient vector is
loaded in the auxiliary page, it can be copied in the active page within a single clock period. Then the
auxiliary page is ready to accept another coefficient vector. Thus, the filter operation is not disturbed during
coefficient reload.
New loadable coefficients arrive at COEFI input to be shifted in the multi-bit Shift register. Every new
coefficient shifts the register contents one step to the left. The coefficients come in natural order, c(0),
c(1),…,c(N-1). After the last coefficient arrives, the coefficients in the auxiliary page are distributed, as
shown in Figure 11 . On the COEF_ON signal the recently entered coefficients are loaded into the active
page. From this time on, they are used as the filter coefficients.
c(0)
c(1)
c(2)
c(3)
c(N-1)
Shift
Register
COEFI
x(i)
z -1
z -1
z -1
z -1
COEF_ON
y(k)
Figure 11 · Reloadable Coefficient Mode.
CoreFIR v8.5 Handbook
15
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