参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 15/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Fully Enumerated Filter
Fully Enumerated Interface Description
Parameters/Generics
The parallel fully enumerated CoreFIR RTL has parameters (Verilog) or generics (VHDL), described in
Table 4 . All the parameters and generics are positive integer types. The table shows the superset of the
parameters used by all FIR filter types, while indicating which parameters the fully enumerated type does not
utilize.
Table 4 · Fully Enumerated Filter Parameter/Generic Descriptions
Parameter Name
Valid
Default
Description
Range
CFG_ARCH
1-4
1
Filter type:
1: Fully Enumerated
2: Folded
3: Polyphase Interpolator
4: Polyphase Decimator
2-2N
TAPS
1
16
Number of taps. For a symmetric filter the valid range is 2 to 2*N (2 to 2*N-
1 for odd symmetry filters), for the other filters the range is 2 to N.
COEF_TYPE
0-1
0
0: Constant coefficients (including multiple coefficient sets)
1: Reloadable coefficients
COEF_SETS
1-16
1
1: Single coefficient set
2-16: Multiple coefficient sets
Valid when constant coefficient type is selected (COEF_TYPE==0)
COEF_SYMM
0-2
0
0: Not symmetric coefficients
1: Symmetric coefficients
2: Anti-symmetric coefficients
COEF_UNSIGN
0-1
0
0: Signed coefficients
1: Unsigned coefficients
COEF_WIDTH
2-18
12
Coefficient bit width. Signed coefficient width ranges from 2 to 18 bits;
unsigned from 2 to 17 bits.
DATA_UNSIGN
0-1
0
0: Signed input data
1: Unsigned input data
DATA_WIDTH
2-18
12
Data bit width. Signed data width ranges from 2 to 18 bits; unsigned from 2
to 17 bits.
SYSTOLIC
0-1
0
? 0: Transposed architecture
? 1: Systolic architecture
Valid when non-symmetric filter is being implemented (COEF_SYMM==1).
Otherwise the Systolic architecture is enforced.
VALID_O
INP_REG
0-1
0-1
1
1
Disable (0) or enable (1) circuitry relevant to detecting initial latency.
Disable (0) or enable (1) input registers. Enabling the registers helps
improving the filter speed.
Die size. The parameter is set through the Libero project settings dialog
FPGA_FAMILY
DIE_SIZE
19, 24
5, 10,
15, 20,
25, 30
19
20
The target FPGA family: SmartFusion2 (19) or IGLOO2 (24)
?
and automatically transfers to the core. If the Libero device selection
changes, the core configuration interface must be invoked and
regenerated RTL.
1.
16
N is a number of physically available MAC’s.
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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