参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 31/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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compute PHY_TAPS filtered results . Then it deasserts the READY signal and waits for the MAC engine to
Folded Filter
When the signal COEF_ON swaps the active and auxiliary pages, generally the PHY_TAPS filtered results
immediately following the COEF_ON are incorrect and need to be discarded. If this is of concern, loop back
the COEF_ON_SLOT signal as COEF_ON.
Data Control and Timing
Input Rate Limitations
Semi-parallel architecture expects the filter input sample rate to be a fraction of the clock rate ( EQ 2 on page
8). Once the number of physical MACs PHY_TAPS is defined, the filter can handle the input data rates up to
the maximum sample frequency of EQ 3 on page 9. This does not mean that every sample interval needs to
satisfy EQ 3 on page 9. The core accepts non-periodic input samples coming with instantaneous frequency
up to the clock frequency.
To relax requirements for the input sample periodicity, the core features the Data FIFO and the READY
signal. A data source can supply data at any frequency as long as the average rate does not exceed the
maximum sample frequency. The FIFO collects PHY_TAPS new input samples, which is sufficient to
start processing to collect data. Depending on the actual input rate the waiting period may vary from a
fraction of the input sample interval to several intervals. For example, if the actual input rate never exceeds
the sample frequency, the waiting period is less than the input sample period. In this case the READY signal
is always active by the time a fresh input sample comes in. In case the data source attempts to supply data,
for example at clock frequency, the READY signal is deasserted for significant interval. The data source
should only assert DATAI_VALID when the READY signal is asserted.
Consider a 12-tap FIR filter with the clock to sample frequency ratio of 4. According to EQ 2 on page 8, the
semi-parallel filter has PHY_TAPS = 12/4 = 3 physical MACs. Figure 27 shows a case where the input
samples are periodic at the fixed timing interval of 4 clocks that satisfies the EQ 3 on page 9.
Note: The READY signal is always active by the time a fresh input sample comes in and thus, can be
neglected in such a case.
CLK
DATAI_VALID
READY
Figure 27 · Fixed Timing Interval Between Input Samples
For the same filter, Figure 28 on page 33 shows the input samples coming at an instantaneous frequency
equal to the clock frequency. The data comes in bursts of PHY_TAPS = 3 samples each. The data source
supplies the samples only when the READY signal is Active.
1
This does not refer to initial warm-up time, which takes more input samples to compute PHY results. Refer
to the Warm-Up Time section on page 39 for details.
32
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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