参数资料
型号: COREFIR-RM
厂商: Microsemi SoC
文件页数: 22/67页
文件大小: 0K
描述: IP MODULE COREFIR
标准包装: 1
系列: *
Fully Enumerated Filter Implementation Details
In many cases there is no need for the filtered sample recipient to know precisely when the valid filtered data
starts. It is sufficient to know that after some initial warm-up time the filter generates the valid data . Table 7
reflects the maximum transition latency values expressed in number of valid input samples required to fill in
the filter delay line.
Table 7 Maximum Transition Latency Values
Transposed
TAPS + 12
Systolic
2 * TAPS + 12
Symmetric
ceiling(1.5 * TAPS) + 12
If the precise transition latency is not of concern, it is better to let the filter run for the time indicated in Table
7 plus the pipeline latency. Every DATAO_VALID flag marks the valid filtered data sample even if the
VALID_O option is disabled.
CoreFIR v8.5 Handbook
23
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