参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 27/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Folded Filter
Signal
In/
Port width, bits
Description
Out
COEF_REF
In
1
Refresh coefficients. Active high. When asserted must last at least one
clock interval.
In Constant coefficient mode, the signal initiates refreshing the coefficient
set stored on the active coefficient memory page.
In Reloadable coefficient mode, the signal initiates reloading coefficients
into the auxiliary page of the coefficient storage.
In Multiple constant Set mode, the signal starts loading into the Auxiliary
page another set of coefficients pointed to by the input COEF_SEL.
COEF_REF_
DONE
Out
1
Done refreshing coefficients. Active high.
Notifies a user that refreshing the constant coefficient set on the active
memory page, or reloading coefficients or loading another multiple set into
the auxiliary page is completed. Now the auxiliary page is ready to become
the active one.
COEF_SEL
In
4
Coefficient set selector. Identifies the pre-programmed fixed coefficient set
to be loaded on the auxiliary page. This port is enabled only when Multiple
coefficients mode is selected.
CLK
NGRST
In
In
1
1
Clock. Rising edge active. The core master clock.
Asynchronous reset. Active low. Resets all internal fabric registers. The
signal is expected to follow the FPGA power-on.
RSTN
In
1
Optional synchronous reset. Active low. Being asserted along with CLK
signal, resets all internal fabric registers.
DATAO
DATAO_VALID
Out
Out
DATA_WIDTH +
COEF_WIDTH +
ceiling(log2TAPS)
1
Data output. The filtered data appear on this port. It is a full precision output.
For example, at 12-bit data, 15-bit coefficients, and 150 taps, the output
width = 12 + 15 + ceil(log2150) = 12 +15 + 8 = 35 bits.
Output data valid. Active high. Indicates that a new output data sample is
present at the FIRO port.
READY
SAMPLE_ID
Out
In
1
Numerical ID width
ID_WIDTH
Active high. The core is ready to accept a fresh input data sample.
Optional numerical ID input. The optional ID is provided by user
synchronously with the DATAI and DATAI_VALID signals.
The port is enabled when support for the ID is enabled (SAMPLEID = 1).
FIRO_ID
Out
Numerical ID width
ID_WIDTH
Optional numerical ID output. CoreFIR accompanies an output sample with
the optional numerical ID that matches the corresponding input sample ID.
The output is valid when support for the ID is enabled (SAMPLEID = 1) and
DATAO_VALID signal is asserted.
COEF_ON_
SLOT
Out
1
Optimized time slot for issuing COEF_ON signal. Active high. The core
generates this optional signal at the times when asserting the COEF_ON
signal does not cause any data or result loss. Once user circuitry is ready to
issue the COEF_ON signal, it should wait for the next COEF_ON_SLOT
pulse and loop it back to the core as the COEF_ON.
28
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
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| COREU1LL-AR | IP MODULE COREU1LL |
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| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
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