参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 19/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Fully Enumerated Filter
Internal filter processing takes place at full precision to reduce truncation/rounding noise and avoid risk of
overflow. The filter output data are presented in full precision as well. If the data and coefficient bit widths
are DATA_WIDTH and COEF_WIDTH, and the number of filter taps = TAPS, the full precision output bit
Output Bit Width = DATA_WIDTH + COEF_WIDTH + ceiling (log 2 TAPS)
EQ 6
Maximum Number of Taps
As the fully enumerated filter utilizes as many MACs as the number of taps, the maximum number of taps
depends on the number of available mathblocks, N, and filter symmetry, as well as coefficient and data bit
width. Table 6 lists the maximum number of taps supported by the selected FPGA devices.
Table 6 Maximum Number of Taps
Symmetry
Bit Width Does Not Exceed
Coefficient
Data
Maximum Number of Taps
Signed
Unsigned
Signed
Unsigned
RTAX
RTAX
M2S050T
2000D
4000D
Non-symmetric
Symmetric
18
18
17
17
18
17
17
16
64
128*
120
240*
72
144*
Note: * In the odd-symmetry filters, the maximum number of taps is one less.
Multiple Coefficients Mode
In this mode, the filter can switch between k pre-configured coefficient sets. Figure 16 shows a single filter
tap in this mode. Other taps are organized and behave similarly. The COEF_SEL input controls a MUX, that
is, selects one of the coefficient sets, but the coefficients are not propagated to the filter yet. This only takes
place when the COEF_ON signal is issued, which loads the newly selected coefficients in the Pipeline
registers.
To improve switching characteristics, issue the COEF_ON signal at least four clock cycles later after
changing the COEF_SEL signal.
c(i)_set_1
COEF_SEL
z -1
Tap i
c(i)_set_2
c(i)_set_3
...
c(i)_set_k
COEF_ON
Figure 16 · A Parallel Filter Tap in Multiple Coefficients Mode
Input Registers
The core inputs that present extensive load for the input signal sources are optionally registered, so that the
user circuitry does not face extensive fan-out. When the parameter INP_REG is set as 1, the core infers a
pair of registers on the following inputs: DATAI, DATAI_VALID, COEFI, COEFI_VALID, COEF_SEL, and
COEF_ON. Figure 17 shows an example of the input register inference. The pairs of registers are used to
enable the synthesis tool (Synplify) to infer replicated register instances and to contain the user input fanout
within the optimal limit. To achieve the best timing results, the global syn_replicate attribute of Synplify
should be used.
20
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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