参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 29/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Folded Filter
CoreFIR
input data
input data valid
DATAI
DATAI_VALID
COEFI
FIRO
DATAO_VALID
READY
output data
output data valid
ready for a new
input data sample
COEFI_VALID
swap active and
auxiliary pages
select coefficient set
COEF_ON
COEF_SEL
load coefficient set
in auxiliary page
optional sample ID
clock
synch reset
asynch reset
COEF_REF
SAMPLE_ID
CLK
RSTN
NGRST
COEF_REF_DONE
FIRO_ID
COEF_ON_SLOT
optional flag of set
loading completion
optional output ID
optional time slot
for COEF_ON
Figure 25 · Folded Multiple Coefficient Set Configuration
Folded Filter Implementation Details
Data Path Bit Width
The core supports signed and unsigned data and coefficients. The core can be configured accordingly. The
output data is unsigned if both input data and coefficients are unsigned. Otherwise the output data is signed.
Input and output data, as well as the coefficients, are integers in two’s complement format.
The core supports signed data and coefficient of 2 to 18 bits. For the unsigned data and coefficients, the
width is limited to 17 bits.
Internal filter processing takes place at full precision to reduce truncation or rounding noise and avoid risk of
overflow. The filter output data are presented at full precision as well. If the data and coefficient bit widths
are DATA_WIDTH and COEF_WIDTH, and the number of filter taps = TAPS, then the full precision output
Output Bit Width = DATA_WIDTH + COEF_WIDTH + ceiling (log 2 TAPS)
EQ 7
Coefficient Modes
Constant Coefficient Mode
In the single set Constant coefficient mode, the coefficients entered at configuration time are copied into the
coefficient ROM. This usually happens once on asynchronous reset signal NGRST, which is normally
asserted upon powering on the FPGA device. A mechanism built into the core runs the process
automatically. No action is required.
Refreshing the contents of the ROM can be done by asserting and deasserting the COEF_REF signal. Then
the core launches the copying sequence again. The core generates the optional pulse, CORE_REF_DONE,
once the initial or secondary copying is completed. The copying takes approximately 4 * TAPS clock
intervals. The core keeps the signal DATAO_VALID deasserted while running the copying sequence.
30
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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