参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 36/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Polyphase Interpolation Filter
Description
Polyphase interpolation combines up sampling and subsequent filtering. The result is similar to the common
meaning of the interpolation that creates additional output samples in between the original ones. The output
sample rate is always an integer multiple of the input rate. The interpolated samples are calculated using the
Interface
Parameters or Generics
Interpolation CoreFIR RTL has parameters (Verilog) or generics (VHDL), as described in Table 11 . All the
parameters and generics are positive integer types. The table shows the superset of parameters used by all
FIR filter types while indicating which parameters the polyphase interpolation type does not utilize.
Table 11 Semi-Parallel CoreFIR Parameter or Generic Descriptions
Parameter Name
Valid
Default
Description
Range
CFG_ARCH
1-4
1
Filter type:
1: Fully Enumerated
2: Folded
3: Polyphase Interpolator
4: Polyphase Decimator.
TAPS
COEF_TYPE
2-1024
0-1
16
0
Number of taps.
0: Constant coefficients (including multiple coefficient sets).
1:Reloadable coefficients.
COEF_SETS
1-16
1
1: Single coefficient set.
2: 16 - Multiple coefficient sets.
Valid when constant coefficient type is selected (COEF_TYPE==0).
COEF_SYMM
COEF_UNSIGN
0-2
0-1
0
0
Interpolation filter does not use the parameter.
0: Signed coefficients.
1: Unsigned coefficients.
COEF_WIDTH
2-18
12
Coefficient bit width. Signed coefficient width ranges from 2 to 18 bits;
unsigned from 2 to 17 bits.
DATA_UNSIGN
0-1
0
0: Signed input data.
1: Unsigned input data.
DATA_WIDTH
2-18
12
Data bit width. Signed data width ranges from 2 to 18 bits; unsigned from 2
to 17 bits.
SYSTOLIC
VALID_O
INP_REG
FPGA_FAMILY
0-1
0-1
0-1
19, 24
0
1
1
19
Interpolation filter does not use the parameter.
Interpolation filter does not use the parameter.
Interpolation filter does not use the parameter.
The target FPGA family: SmartFusion2 (19) or IGLOO2 (24). The
parameter is set through the Libero SoC project settings dialog and
CoreFIR v8.5 Handbook
37
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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