参数资料
型号: COREFIR-RM
厂商: Microsemi SoC
文件页数: 18/67页
文件大小: 0K
描述: IP MODULE COREFIR
标准包装: 1
系列: *
Fully Enumerated Filter Implementation Details
CoreFIR
input data
input data valid
coefficient
coefficient valid
switch to loaded coefficients
DATAI
DATAI_VALID
COEFI
COEFI_VALID
COEF_ON
FIRO
DATAO_VALID
output data
output data valid
COEF_SEL
clock
synch reset
asynch reset
CLK
RSTN
NGRST
Figure 14 · Parallel Filter Reloadable Coefficient Configuration
CoreFIR
input data
input data valid
DATAI
DATAI_VALID
FIRO
DATAO_VALID
output data
output data valid
COEFI
COEFI_VALID
select coefficient set
switch to selected set
clock
synch reset
asynch reset
COEF_SEL
COEF_ON
CLK
RSTN
NGRST
Figure 15 · Parallel Filter Multiple Coefficients Configuration
Fully Enumerated Filter Implementation Details
Data Path Bit Width
The core supports signed and unsigned data and coefficients. The core can be configured accordingly. The
output data is unsigned if both input data and coefficients are unsigned. Otherwise the output data is signed.
Input and output data, as well as the coefficients are integers in two’s complement format.
The core supports signed data and coefficients of 2 to 18 bits. For the unsigned data and coefficients, the
width is limited to 17 bits. With symmetric filter implementation, the maximum data width is reduced to
17 bits for signed data, and to 16 bits for unsigned data.
CoreFIR v8.5 Handbook
19
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