参数资料
型号: COREFIR-RM
厂商: Microsemi SoC
文件页数: 26/67页
文件大小: 0K
描述: IP MODULE COREFIR
标准包装: 1
系列: *
Folded Filter Interface
Ports
The semi-parallel FIR filter symbol is shown in Figure 22 . Table 10 provides the port definitions for the core.
CoreFIR
DATAI
DATAI_VALID
COEFI
COEFI_VALID
COEF_ON
COEF_SEL
COEF_REF
SAMPLE_ID
CLK
FIRO
DATAO_VALID
READY
COEF_REF_DONE
FIRO_ID
COEF_ON_SLOT
RSTN
NGRST
Figure 22 · CoreFIR I/O Ports
The pinout of Figure 22 is a superset of all possible folded filter ports. In every configuration, only a subset of
these is used.
Table 10 Folded CoreFIR Filter In/Out Signals
Signal
In/
Port width, bits
Description
Out
DATAI
In
Input data width,
Input data to be filtered.
DATA_WIDTH
DATAI_VALID
In
1
Input data valid. Active high. When the signal is active, the input data
sample is loaded into the FIR Filter. DATAI_VALID should not be active, if
READY signal is inactive. Input data samples coming while the READY
signal is inactive are ignored.
COEFI
In
Coefficient bit width,
COEF_WIDTH
Coefficient input. The coefficients are to be loaded sequentially, one by one.
The coefficients are loaded on an Auxiliary memory page. They replace the
current coefficients all at once on COEF_ON signal. This port is enabled
only when Reloadable coefficient mode is selected.
COEFI_VALID
In
1
Coefficient valid. Active high. When the signal is active, a coefficient is
loaded into the FIR Filter. This port is enabled only when Reloadable
coefficient mode is selected.
COEF_ON
In
1
Coefficients on. Active high. Swaps Active and Auxiliary pages of the
coefficient memory.
In Multiple constant set mode (COEF_TYPE==0, COEF_SETS>1), the
signal replaces the current coefficient set with the one loaded in the auxiliary
page.
In Reloadable coefficient mode (COEF_TYPE == 1), the signal makes the
filter start using coefficients recently loaded in the auxiliary page.
The port is enabled in Multiple set and Reloadable modes. In the Constant
coefficient mode (COEF_TYPE==0, COEF_SETS==0), CoreFIR starts
using the coefficients shortly after FPGA is powered.
CoreFIR v8.5 Handbook
27
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