参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 38/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Interface
The pinout of Figure 34 is a superset of all possible ports. In every configuration only a subset of these is
used.
Table 12 FIR In/Out Signals
Signal
DATAI
In/Out
In
Port Width, Bits
Input data width,
Input data to be filtered.
Description
DATA_WIDTH
DATAI_VALID
In
1
Input data valid. Active high. When the signal is active, the input
data sample is loaded into the FIR filter. DATAI_VALID should not
be active, if READY signal is inactive. Input data samples coming
while the READY signal is inactive are ignored.
COEFI
In
Coefficient bit width,
COEF_WIDTH
Coefficient input. The coefficients are to be loaded sequentially,
one by one. This port is enabled only when reloadable coefficient
mode is selected.
COEFI_VALID
In
1
Coefficient valid. Active high. When the signal is active, a
coefficient is loaded into the FIR filter. This port is enabled only
when reloadable coefficient mode is selected.
COEF_REF
In
1
Refresh coefficients. Active high.
In Reloadable coefficient mode, the signal initiates reloading
coefficients into auxiliary page of the coefficient storage.
In Multiple constant set mode, the signal starts loading into the
auxiliary page another set of coefficients pointed to by the input
COEF_SEL.
COEF_REF_
DONE
Out
1
Done refreshing coefficients. Active high.
Notifies that reloading coefficients or loading another Multiple set
into the auxiliary page is completed. Now the auxiliary page is
ready to become the active one.
COEF_SEL
In
4
Coefficient set selector. Identifies the pre-programmed fixed
coefficient set to be loaded on the auxiliary page. This port is
enabled only when Multiple coefficients mode is selected.
COEF_ON
In
1
Coefficients on. Active high. Swaps active and auxiliary pages of
the coefficient memory.
In Multiple constant set mode (COEF_TYPE==0, COEF_SETS>1),
the signal replaces the current coefficient set with the one loaded in
the auxiliary page.
In Reloadable coefficient mode (COEF_TYPE == 1), the signal
makes the filter start using coefficients recently loaded in the
auxiliary page.
The port is enabled in Multiple set and Reloadable modes. In
Constant coefficient mode (COEF_TYPE==0, COEF_SETS==0),
CoreFIR starts using the coefficients shortly after FPGA is
powered.
CLK
NGRST
In
In
1
1
Clock. Rising edge active. The core master clock.
Asynchronous reset. Active low. Resets all internal fabric registers.
The signal is expected to follow the FPGA power-on.
RSTN
In
1
Optional synchronous reset. Active low. Being asserted along with
CLK signal, resets all internal fabric registers.
CoreFIR v8.5 Handbook
39
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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