参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 32/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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PHY_TAPS N+7
+
Folded Filter Implementation Details
CLK
DATAI_VALID
READY
Figure 28 · Bursts of the Input Samples
Input and Output Time Domains
The core accepts input tight to the core CLK signal. The average data input rate must satisfy EQ 3 on page
9. The filtered results come out of the FIRO port in bursts of PHY_TAPS samples each, one output sample
per clock interval. The signal DATAO_VALID accompanies the valid output samples.
Figure 29 shows the filter output bursts for the filter example described in the section “ Input Rate
CLK
DATAO_VALID
FIRO
Figure 29 · Filtered Results
Filter Latency
Once the FIFO collected PHY_TAPS new input samples and the MAC engine is ready for processing, the
FIFO bursts out all the samples necessary to compute PHY_TAPS filtered results. It takes the MAC engine
N + 7 clock intervals of processing time for the filter to start generating PHY_TAPS results, one per clock
interval. Refer to the “ Input Rate Limitations ” section on page 32 as an example of a fixed input rate. The
rising edge of the COEF_ON_SLOT output signal marks the beginning of the processing time ( Figure 30 ),
and the falling edge of the READY signal marks the moment when FIFO finishes collecting PHY_TAPS
fresh data samples. The MAC engine is ready to process fresh PHY_TAPS input samples as soon as the
Data FIFO finishes collecting them. The overall latency from the moment when FIFO started collecting the
Sample frequency Clock frequency EQ 8
CoreFIR v8.5 Handbook
33
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| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
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| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
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| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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