参数资料
型号: COREFIR-RM
厂商: Microsemi SoC
文件页数: 8/67页
文件大小: 0K
描述: IP MODULE COREFIR
标准包装: 1
系列: *
Filter Types
MAC Engine
x(i)
Data FIFO
Z -1
Z -1
Coefficient
ROM
ACC
ACC
ACC
Output
Maximum sample frequency = Clock frequency ? (PHY_TAPS)/N
Figure 3 · Semi-Parallel FIR Filter Functional Block Diagram
EQ 3
There is no need to indicate whether the single rate filter is to be fully enumerated or folded. It is only
required to indicate the clock, and input sample frequencies. If the clock to sample rate ratio is not less than
2, CoreFIR automatically generates the folded type. If the fully enumerated type is needed, the same value
for the clock and sample frequencies must be entered.
Polyphase Interpolation Filter
The primary reason for interpolation is to increase the sampling rate at the output of one system so that
another system operating at a higher sampling rate can input the signal.
Through calculations on existing data, interpolation fills in missing information between the samples of a
signal. Interpolation increases a sample rate by an integer factor L.
The architecture calculates output using N/L multipliers, where N is a number of filter coefficients and L is an
Interpolation factor, to get an overall computational saving of (N - N/L) compared to the straightforward
???? ( ?? ) = ∑ ???? ?? ( ?? ? ?? ) ? ? ( ?? ) ,
implementation.
At every clock interval the architecture computes and accumulates several products, as shown in EQ 4 .
EQ 4
Where, P = 0 to (L-1) and j = P, P+ (L-1), P+ 2*L – 1, 3*L – 1,…N
Figure 4 on page 10 provides an example of the polyphase interpolation filter architecture for a TAP of 16
and Interpolation factor of 4. The interpolator contains distributed coefficient ROM, one storage per physical
filter tap. In Figure 4 on page 10, the first storage keeps coefficients h 0 to h 3 , the second storage keeps
coefficients h 4 to h 7, and so on.
CoreFIR v8.5 Handbook
9
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