参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 25/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页当前第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页
Folded Filter
Parameter Name
Valid
Default
Description
Range
INP_REG
FPGA_FAMILY
0-1
19, 24
1
19
Folded filter does not use the parameter.
The target FPGA family: SmartFusion2 (19) or IGLOO2 (24). The
parameter is set through the Libero SoC project settings dialog and
automatically transfers to the core.
DIE_SIZE
5, 10, 15,
20, 25, 30
20
Die size. The parameter is set through Libero project settings dialog and
automatically transfers to the core. If the Libero device selection
changes, you must invoke the core configuration interface and
regenerate RTL.
COEF_RAM
0-1
0
0: Build Coefficient ROM out of fabric resources.
1: Build Coefficient ROM using RAM blocks available on a chip.
DATA_RAM
0-1
0
0: Build Data FIFO out of fabric resources.
1: Build Data FIFO using RAM blocks available on a chip.
SAMPLEID
0-1
0
Disable (0) or enable (1) optional support for attaching numerical ID to
input and output samples.
ID_WIDTH
1-10
5
Numerical ID bit width. Valid when the ID support is enabled (SAMPLEID
= 1).
URAM_MAXDEPTH
0
2, 4, 8,
16, 32, 64
Micro RAM depth upper limit. The parameter limits the depth of uRAM to
be taken for data and/or coefficient storage. Once either or both
COEF_RAM or DATA_RAM parameters are set, the core uses on-chip
RAM blocks to implement appropriate storage. If the required storage
depth does not exceed the URAM_MAXDEPTH value, the Micro RAM is
used, otherwise the core utilizes the Large RAM blocks.
L
M
2-512
2-512
2
2
Folded filter does not use the parameter.
Folded filter does not use the parameter.
Other User Parameters
Table 9 lists two more parameters which must be configured for the core. They are not limited to integer
numbers, as they are not used by the RTL directly. The user interface converts two user parameters, Input
sample frequency and clock frequency, to the single RTL parameter PHY_TAPS.
Table 9 · Other CoreFIR User Parameters
Parameter Name
SAMPLE_RATE
CLOCK_RATE
26
Valid Range
0.001 – 75.0
0.01 – 150.0
Default
1.0
10.0
Description
Input data sample rate, Msamples/sec. A real number.
Clock frequency, MHz. A real number.
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
发布紧急采购，3分钟左右您将得到回复。