参数资料
型号: COREFIR-RM
厂商: Microsemi SoC
文件页数: 33/67页
文件大小: 0K
描述: IP MODULE COREFIR
标准包装: 1
系列: *
Folded Filter
CLK
DATAI_VALID
READY
FIFO finishes collecting PHY new input
samples
FIFO starts collecting PHY new input samples
COEF_ON_SLOT
MAC Engine starts processing new samples
Processing Delay = N+7 clock intervals
DATAO_VALID
FIRO
Figure 30 · Filter Latency Example at Fixed Input Rate
Latency calculation for the case when momentary input rate may exceed maximum sample frequency of
EQ 3 on page 9 is more complicated; as by the time the FIFO is filled with new samples, the MAC engine
can still be busy processing the previous burst ( Figure 31 ). Therefore, processing starts on the rising edge of
a COEF_ON_SLOT pulse, following a FIFO collecting period.
CLK
DATAI_VALID
READY
FIFO is collecting PHY
COEF_ON_SLOT
new input samples
MAC Engine starts processing new samples
Processing Delay = N+7 clock intervals
DATAO_VALID
FIRO
Figure 31 · Filter Latency Example at High Momentary Input Rate
Optional Numeric ID
The core provides a mechanism for attaching numerical IDs to the input and output samples to know which
filtered sample corresponds to certain portion of the input data. From EQ 1 on page 5 , it is seen that every
filtered output y(k) is a result of convolution between the filter coefficients c(0) to c(N-1) and a range of data
samples from x(k-N+1) to x(k) . The ID helps to associate output index with the input data samples from k-
N+1 to k . The output ID carries the input ID attached to the first input sample of the range, namely k-N+1 (to
make output indices match the formula of the EQ 1 on page 5 , N-1 must be added to the actual output
index). A user is required to supply the ID to the SAMPLE_ID port simultaneously with the DATAI_VALID
and DATAI signals ( Figure 32 on page 35 ).
34
CoreFIR v8.5 Handbook
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