参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 50/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Data Path Bit Width
CoreFIR
Input data
Input data valid
DATAI
DATAI_VALID
FIRO
FIRO_VALID
output data
output data valid
COEFI
COEFI_VALID
Select coefficient set
COEF_SEL
Optional
refresh coefficient set
Enable newly loaded
coefficient set
Clock
Synch reset
Asynch reset
COEF_REF
COEF_ON
CLK
RSTN
NGRST
COEF_REF_DONE
Optional flag of set
loading completion
Figure 45 · Multiple Coefficient Set Configuration
Data Path Bit Width
The core supports signed and unsigned data and coefficients. The core can be configured accordingly. The
output data is unsigned, if both input data and coefficients are unsigned. Otherwise the output data is
signed. Input and output data, as well as the coefficients, are integers in two’s complement format.
The core supports signed data and coefficient of 2 to 18 bits. For the unsigned data and coefficients, the
width is limited to 17 bits. With symmetric filter implementation, the maximum data width is reduced to 17
bits for signed data, and 16 bits for unsigned data.
Internal filter processing takes place at full precision to reduce truncation or rounding noise and avoid risk of
overflow. The filter output data are presented in full precision as well. If the data and coefficient bit widths
are DATA_WIDTH and COEF_WIDTH, and the number of filter taps = TAPS, then the full precision output
Output Bit Width = DATA_WIDTH + COEF_WIDTH + ceiling(log 2 TAPS)
EQ 10
Coefficient Modes
Constant Coefficient Mode
In single set Constant coefficient mode, the coefficients entered at configuration time are copied into the
coefficient ROM. The initial copying happens once on asynchronous reset signal NGRST, which normally is
asserted upon powering on the FPGA device. A mechanism built into the core runs the process
automatically. No action is required.
Assert the COEF_REF signal to refresh the contents of the ROM, if required. The core runs the copying
sequence again. The core generates the optional pulse, CORE_REF_DONE, once the initial or subsequent
copying is completed. The copying takes approximately 8 * TAPS clock intervals. The core keeps the signal
DATAO_VALID deasserted until copying is completed.
CoreFIR v8.5 Handbook
51
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PDF描述 |
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相关代理商/技术参数 |
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| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
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| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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