参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 7/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Sample frequency
comprised of Z blocks, and an output multiplexer. After filling in a delay line with necessary input samples,
Introduction
Filter Types
Depending on a user configuration, CoreFIR generates one of the supported filter types.
Fully Enumerated Filter
The single rate parallel FIR filter provides the highest input sampling rate processing. The performance of
the parallel filter expressed as the maximum input sample frequency equals the maximum clock rate, that is,
the filter can process a sample per clock interval. Figure 1 on page 5 shows an accurate functional model of
the fully enumerated filter. The filter utilizes as many MAC blocks as the number of coefficients also called
the number of taps. The largest filter (in terms of number of coefficients) a particular FPGA device can carry
is limited by the number of available MAC blocks.
Folded Filter
This one is a single-rate semi-parallel filter. In many practical cases, the filter input sample rate equals only a
fraction of the FPGA clock rate. Then the processing power of the MAC block can be re-used to process
more than a single filter tap. At every clock interval, the semi-parallel filter computes and accumulates
several products of EQ 1 on page 5. In a few clocks before a next input sample comes in, all N products are
accumulated.
The number PHY_TAPS of the products the filter engine computes at every clock interval is determined
based on required number of taps N, input sample frequency, and the FPGA clock frequency as follows:
Clock frequency EQ 2
Figure 3 on page 14 shows the folded filter simplified functional block diagram. Input data samples come to
a Data FIFO that collects a number of samples sufficient to compute PHY_TAPS products each clock
interval. The Coefficient ROM stores N coefficients. The MAC engine has PHY_TAPS MACs, a delay line
-1
the MAC engine reads N data samples simultaneously with N coefficients to compute PHY_TAPS filtered
results. After the computation is over, the PHY_TAPS results are collected in PHY_TAPS accumulators. The
multiplexer (MUX) puts them out one by one.
8
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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