参数资料
| 型号： | COREFIR-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 43/67页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFIR |
| 标准包装： | 1 |
| 系列： | * |
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Polyphase Interpolation Filter
Reloadable Coefficients
Similarly to Multiple constant set mode, the coefficient ROM contains two pages, Active and Auxiliary. While
the filter engine keeps using coefficients stored in the Active page, user circuitry can download a new
reloadable set of coefficients on the auxiliary page. To do so, assert and deassert COEF_REF signal and
supply the new reloadable coefficients and validity bits to the ports COEFI and COEFI_VALID, respectively.
The coefficients must be supplied in the natural order: h 0 , h 1, and so on. Once TAPS number of coefficients
is loaded, the core issues the optional signal COEF_REF_DONE. For the filter MAC engine to switch to the
just loaded coefficients, pulse the COEF_ON signal that swaps the pages. The swapping takes up to four
clock intervals. The input data samples coming after that time will be properly processed.
After initial power-up, the active page does not contain any meaningful coefficients. Therefore, the core does
not produce a valid result until the auxiliary page gets filled with a valid set of reloadable coefficients and
becomes the active page after the COEF_ON signal comes in Timing and Controls.
Data Rate Control
By definition, the input sample rate of the interpolation filter is lower than its output rate. Often the output rate
equals the FPGA clock rate used. Provided Fclk is the clock frequency, the input sample frequency is Fclk/L.
The relation between input and output samples is simple: upon receiving an input sample, the filter
generates L output samples. These appear at the filter FIRO output after certain latency discussed below.
Once the filter receives another input sample, it lowers the READY signal to let a signal source know it is
going to be busy computing interpolation samples. In L-1 clock cycles, the filter asserts the READY signal
back to let the data source know it is ready to receive the next input sample. Figure 39 and Figure 40 show
the examples of the READY signal for a filter with interpolation factor L = 3. The filter requires L = 3 clock
intervals to output the interpolated samples. In other words, the interpolation cycle here equals three clock
cycles.
The data source issues a fresh sample once per four clock intervals that is the data interval is larger than the
interpolation cycle factor L, as shown in Figure 39 . The signal READY goes low at the next clock cycle after
the active DATAI_VALID signal and stays Low for two clock cycles marked busy. Then it goes High,
signaling to the data source it is ready to accept another valid data sample. The data source can take as
much time as it needs to generate the fresh data sample.
CLK
DATAI_VALID
READY
busy
busy
DATAI
Valid data
Figure 39 · Input Sample Interval Exceeds Interpolation Cycle
Figure 40 shows an example where the data source is permanently ready after initialization. Once the
DATAI_VALID goes High, the READY signal lets the first data sample to get in, and goes low on the front
edge of the next clock pulse. It stays low for two clock cycles marked busy and then goes High for one clock
interval. In such a simple case, the DATAI_VALID can be connected to VCC, and the data source only
needs to refresh data simultaneously with the negative edge of the READY signal.
The core ignores input data samples coming when the READY signal is Low.
44
CoreFIR v8.5 Handbook
相关PDF资料 |
PDF描述 |
|---|---|
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
| CP2-GSA-L | CONN SHIELD LOWER TYPE A 22 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFIR-UR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-XX | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREMP7 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7 |
| COREPCI-AN | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
| COREPCI-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41 |
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