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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 11/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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VCO
The VCO oscillator frequency covers from 40 to 203MHz.
VCO Rear-end Counter
The VCO output is frequency divided to 1/1, 1/2, 1/4 or 1/8 by switching 2 bits of control register.
The operating range can be expanded to 5 to 203MHz by combining the counter with a VCO frequency divider.
Feedback Programmable Counter
This counter can be set as desired from 256 to 4096 using 12 bits.
Frequency divisions = (m + 1)
× 8 + n, n : 3 bits (VCO DIV bits 0 to 2), m : 9 bits (VCO DIV bits 3 to 11)
When the register value is changed, the new setting is actually loaded to the counter when the counter value
becomes “all 0”.
Clock Output
When SYNC input is positive polarity, the clock is regenerated in sync with the rising edge of the sync signal.
The clock output delay time can be changed in the range of 8/32 to 48/32 CLK using 6 bits of control register.
(See the I/O Timing Chart.)
Output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL output
can also be turned off independently.
1/2 Clock Output
Reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (See the I/O
Timing Chart.)
Both odd and even output are TTL and PECL output. TTL output can also be turned off independently.
Register : DIV 1, 2, 4, 8 bit 1
0
1
Register : DIV 1, 2, 4, 8 bit 0
0
1
0
1
Counter frequency divisions
1/11/21/41/8
Register : Clock Enable
1
0
Clock output status
ON
OFF
Register : Clock Enable
1
0
Clock output status
ON
OFF
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