参数资料
型号: CXA3266Q
元件分类: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, 0.12 MHz, PQFP48
封装: PLASTIC, QFP-48
文件页数: 16/62页
文件大小: 929K
代理商: CXA3266Q
CXA3266Q
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Readout Circuit (during test mode)
The control register contents can be read by serial data from SEROUT.
(See the Control Register Timing Chart.)
Programmable Counter Output (during test mode)
The programmable counter output is TTL output from the DIVOUT pin.
(See the I/O Timing Chart.)
This output is normally not used.
TLOAD Input (during Test Mode)
This control signal forcibly loads the control register contents to the programmable counter.
This signal is normally not used.
VCO Input (during Test Mode)
This is the programmable counter test signal input pin.
This pin can be switched internally by the MUX circuit.
TTL and PECL input are possible.
This pin is normally not used.
Register : Read out power
0
1
Readout status
Function OFF
Function ON
Register : DIVOUT Enable
0
1
DIVOUT output status
OFF
ON
TLOAD
H
L
Forced load control status
Function OFF
Function ON
Register : VCO By-pass
1
0
Input status
Internal VCO
External input
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