- 您现在的位置：买卖IC网 > PDF目录170341 > CXA3266Q PHASE LOCKED LOOP, 0.12 MHz, PQFP48 PDF资料下载
参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 19/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
CXA3266Q
- 26 -
Read Mode
Data can be transferred from the shift register to the data register only when SENABLE is High.
Binary data can be read from the data register by inputting SCLK when SENABLE is High. Data is loaded from
the data register to the SCAN PATH circuit each time one clock is input to SCLK, and is output sequentially
from the register read no. 1 data (VCODIV bit 7) through the SEROUT pin. When the 42nd SCLK clock pulse
is input, the register read no. 42 data (VCO By-pass) is output. Then, when the 43rd clock pulse is input to
SCLK, the output returns to the register read no. 1 data (VCODIV bit 7) and the data output is repeated. Also,
the data output from the SCAN PATH circuit is automatically reloaded even when the shift register data is
changed during data output.
Note) Since all registers do not have 8 bits, only the valid bits of each register are loaded to the SCAN PATH
circuit. (See the Control Register Table for the actual register read no.)
Block Diagram during Read Mode
Timing Chart during Read Mode
SEROUT
I/P SHIFT REGISTER, 11 BITS
8 BITS DATA
3 BITS ADDRESS
CLK
NEN
TR
EN
CLK
SCLK
SENABLE
7 DATA REGISTERS (42 LATCHES).
REGISTERS ARE DIFFERENT LENGTHS
UP TO 8 BITS
SCAN PATH, 1 ELEMENT PER REGISTER BIT
TNENS
TNENH
READ NO. 1
READ NO. 2
READ NO. N
N
1
2
SENA
SEROUT
SCLK
相关PDF资料 |
PDF描述 |
|---|---|
| CXA3621GE | SPECIALTY ANALOG CIRCUIT, PBGA30 |
| CXB1140Q | 1000 SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, MQFP32 |
| CXK77B3640GB-4 | 128K X 36 LATE-WRITE SRAM, 5.3 ns, PBGA119 |
| CXK77P18L80AGB-4A | 512K X 18 LATE-WRITE SRAM, 3.8 ns, PBGA119 |
| CXO-199-148.5MHZ | CRYSTAL OSCILLATOR, SINE OUTPUT, 148.5 MHz |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CXA3268AR | 制造商:SONY 制造商全称:Sony Corporation 功能描述:Driver/Timing Generator for Color LCD Panels |
| CXA3271AGE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Fingerprint Sensor |
| CXA3271GE | 制造商:SONY 制造商全称:Sony Corporation 功能描述:Fingerprint Sensor |
| CXA3272R | 制造商:SONY 制造商全称:Sony Corporation 功能描述:CXA3272R |
| CXA3275Q | 制造商:SONY 制造商全称:Sony Corporation 功能描述:PLL/OSC/MIX IC for Digital Tuner |
发布紧急采购，3分钟左右您将得到回复。