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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 13/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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Delay Sync Output
The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK
regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can be used as the
reset signal for the system timing circuit.
The rear edge of the delay sync pulse is latched by the CLK regenerated by the PLL. This relationship is
undefined for one clock as shown in the Timing Chart.
The delay sync output delay time can be varied in two stages. First, the delay time can be varied in the range
of 8/32 to 48/32 CLK using 6 bits of control register, and then in the range of 2 to 5 CLK using 2 bits of control
register. In other words, the total delay time is ((8/32 to 48/32) + (2 to 5)) CLK. (See the I/O Timing Chart.)
DSYNC output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL
output can also be turned off.
Programmable Counter TTL Output Switching
Output (PECL, TTL) from DSYNC output is possible by switching of control register.
Delay Sync Output Width (DSYNC By-pass = 0)
Delay sync output pulse width can be varied to 1, 2, 4, or 8CLK by switching 2 bits of control register.
Delay Sync Output Delay (DSYNC By-pass = 0)
DIVOUT output delay from delay sync output can be varied to 4CLK or 5CLK by switching of control register.
Register : Clock Enable
1
0
Clock output status
ON
OFF
Lower delay line
FINE DELAY bits 0 to 5
000111
001000
101111
Delay time
8/32CLK
9/32CLK
48/32CLK
Upper delay line
COARSE DELAY bits 0 to 1
00
01
10
11
Delay time
2CLK
3CLK
4CLK
5CLK
Register : DSYNC POL
1
0
DSYNC output polarity
Positive
Negative
Register : DSYNC By-pass
0
1
Output status from DSYNC
DIVOUT output
DSYNC output
Register : DSYNC WIDTH
00
01
10
11
DSYNC width
1CLK
2CLK
4CLK
8CLK
Register : DSYNC DELAY
0
1
Delay time
4CLK
5CLK
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