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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 43/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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CXA3266Q and Sony ADC (Demultiplex Mode) Timing : 160MHz specification
The CXA3266Q and CXA3276Q/CXA3286R timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
For the A/D converters
Clock input vs. reset input
The setup time is T – 1.1ns and the hold time is 0.3ns, satisfying the A/D converter specifications.
For the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. 1/2 clock output timing
The setup time is T – 4.0ns and the hold time is T – 3.0ns. (These timings also include combinations of
three A/D converters from different lots, and are defined for all operating temperatures and all operating
supply voltages. See the CXA3276Q/CXA3286R data sheets for a detailed description.)
For the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3266Q vs. 1/2 clock output of A/D converter
The setup time is T – 3.2ns and the hold time is T – 3.7ns.
CLK (PECL)
out
T
2.8 to 6.2ns
0.3 to 1.1ns
3.0 to 6.5ns
Thold min.
T - 3.7ns
Tsetup min.
T - 3.2ns
Tsetup min.
T - 4.0ns
Thold min.
T - 3.0ns
DSYNC (TTL)
out
1/2CLK (PECL)
out
1/2CLK (TTL)
out
DATA (TTL)
out
CXA3276Q
CXA3286R
CXA3266Q
See the CXA3276Q and CXA3286R data sheets.
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相关代理商/技术参数 |
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| CXA3268AR | 制造商:SONY 制造商全称:Sony Corporation 功能描述:Driver/Timing Generator for Color LCD Panels |
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| CXA3271GE | 制造商:SONY 制造商全称:Sony Corporation 功能描述:Fingerprint Sensor |
| CXA3272R | 制造商:SONY 制造商全称:Sony Corporation 功能描述:CXA3272R |
| CXA3275Q | 制造商:SONY 制造商全称:Sony Corporation 功能描述:PLL/OSC/MIX IC for Digital Tuner |
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