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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 3/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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29 CLK/2L
O
PECL
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-down
resistor.
When not used, connect to PECLVCC
without connecting a pull-down resistor.
30 CLK/2H
O
PECL
1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-down
resistor.
When not used, connect to PECLVCC
without connecting a pull-down resistor.
31 CLKL
O
PECL
Inverted clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-down
resistor.
When not used, connect to PECLVCC
without connecting a pull-down resistor.
32 CLKH
O
PECL
Clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-down
resistor.
When not used, connect to PECLVCC
without connecting a pull-down resistor.
33 DSYNCL OPECL
Delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pull-down
resistor.
When not used, connect to PECLVCC
without connecting a pull-down resistor.
34 DSYNCH OPECL
Inverted delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pull-down
resistor.
When not used, connect to PECLVCC
without connecting a pull-down resistor.
35 VBB
O
PECLVCC
– 1.7V
PECL reference voltage.
When used, ground this pin to the
ground pattern with a 0.1
F ceramic chip
capacitor as close to the pin as possible.
44 IREF
—
1.2V
Charge pump current preparation.
Connect to GND via an external
resistor (3.0k
).
Ground this pin to the ground pattern
with a 0.1
F ceramic chip capacitor
as close to the pin as possible.
Pin
No.
Symbol I/O
Reference
voltage level
Equivalent circuit
Description
IOGND
IOVCC
PECLVCC
29
30
31
32
33
34
PECLVCC
IOGND
35
IRVCC
IRGND
IOGND
44
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